- SpaceX (Sunnyvale, CA)
- Sr . SOC / ASIC Physical Design Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where humanity is out ... the ultimate goal of enabling human life on Mars. SR . SOC / ASIC PHYSICAL ...and weekends as needed COMPENSATION AND BENEFITS: Pay range: Physical Design Engineer/ Senior : $170,000.00 - $230,000.00/per year… more
- SpaceX (Irvine, CA)
- Sr . SOC / ASIC Timing Signoff & Front-End Implementation Engineer (Silicon Engineering) Irvine, CA Apply SpaceX was founded under the belief that a future ... the ultimate goal of enabling human life on Mars. SR . SOC / ASIC TIMING SIGNOFF &...ownership throughout the entire project cycle (RTL, synthesis, and physical implementation) + Analysis of clock domain crossing paths… more
- SpaceX (Irvine, CA)
- Sr . ASIC Design Engineer (Silicon Engineering) Irvine, CA Apply SpaceX was founded under the belief that a future where humanity is out exploring the stars is ... the ultimate goal of enabling human life on Mars. SR . ASIC DESIGN ENGINEER (SILICON ENGINEERING) At...problems including clock domain crossings and power optimization + ASIC / SoC system integration experience + Experience with… more
- NVIDIA (Santa Clara, CA)
- NVIDIA is seeking an outstanding Senior ASIC Design Engineer to design and implement the world's leading SoC 's and GPU's. This position offers the ... Deliver a synthesis/timing clean design while working with the physical design team to ensure a routable and physically...and Digital Systems design. + A deep understanding of ASIC design flow including RTL design, verification, logic synthesis,… more
- Cisco (San Jose, CA)
- …Your Impact You will be part of the development organization as an ASIC Engineering Technical Leader with primary focus on RTL Design. Key responsibilities: * ... bugs and close code coverage. * Work closely with physical design team to close design timing and place-and-route...plus. * Experience with Integrating 3rd party IP's into SoC is desirable * Scripting experience (Python, Perl, TCL,… more
- NVIDIA (Santa Clara, CA)
- …plans for NVIDIA's next generation of high-performance IPs for CPU, GPU and SOC designs. + Owning static timing analysis and convergence of high-performance designs. ... MS (or equivalent experience) with 3+ years' experience in ASIC Design and Timing + Hands-on experience in STA...with cross-functional teams. + Strong understanding of timing and physical design fundamentals Ways to stand out from the… more
- Qualcomm (San Diego, CA)
- …decoupling capacitance scheme. + Work with system designers, design verification and physical design teams to define, implement, and verify power delivery solutions. ... degree in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience. OR Master's degree… more
- Broadcom (Irvine, CA)
- …guarantee production quality for "first spin" silicon, we in the CSG ASIC team combine production workload-focused test harnesses with large scale emulation ... resources to provide extensive system level ASIC test coverage prior to first silicon fab. Our...core bench level simulations. We are looking for a Sr . level system software / firmware engineer, with broad… more
- Microsoft Corporation (Santa Clara, CA)
- …in your career. **Responsibilities** + Lead key components of functional validation of complex ASIC SOC using UVM/C test bench + Perform pre-silicon SoC ... are looking for passionate, high-energy engineers to help achieve that mission. As a Senior Silicon Engineer - ASIC verification in the Data Processing Unit team… more
- The Boeing Company (Huntington Beach, CA)
- …for someone to join a team committed to understanding and improving state-of-the-art SoC and ASIC designs for Quantum Systems Microelectronics (QSM), a part ... is looking for a **Cryogenic Integration Engineer (Associate, Mid-Level or Senior )** based out of **Huntington Beach, CA.** Within BR&T, Boeing's Microelectronics… more
- Qualcomm (San Diego, CA)
- …and experience is a must. Debug and Trace, Reliability Availability Serviceability, SOC IP, bus, cache coherency, interrupt, system firmware and kernel knowledge are ... processor core and system compliance certification, modeling and verification. Additionally, physical design and government affairs background is a plus. **Minimum… more