- SpaceX (Irvine, CA)
- Sr . SOC / ASIC Timing Signoff & Front-End Implementation Engineer (Silicon Engineering) Irvine, CA Apply SpaceX was founded under the belief that a future ... the ultimate goal of enabling human life on Mars. SR . SOC / ASIC TIMING ...COMPENSATION & BENEFITS: Pay range: Synthesis and Front-End STA Engineer/ Senior : $160,000.00 - $220,000.00/per year Your actual level and… more
- SpaceX (Sunnyvale, CA)
- Sr . SOC / ASIC Physical Design Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where humanity is out ... to make this possible, with the ultimate goal of enabling human life on Mars. SR . SOC / ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're… more
- SpaceX (Irvine, CA)
- Sr . ASIC Design Engineer (Silicon Engineering) Irvine,... clean design + Participate in all phases of ASIC and/or FPGA design flow (eg synthesis, timing ... the ultimate goal of enabling human life on Mars. SR . ASIC DESIGN ENGINEER (SILICON ENGINEERING) At...problems including clock domain crossings and power optimization + ASIC / SoC system integration experience + Experience with… more
- NVIDIA (Santa Clara, CA)
- …plans for NVIDIA's next generation of high-performance IPs for CPU, GPU and SOC designs. + Owning static timing analysis and convergence of high-performance ... experience or MS (or equivalent experience) with 3+ years' experience in ASIC Design and Timing + Hands-on experience in STA tools, ECO implementation, and … more
- Amazon (San Diego, CA)
- …role you will: . Work closely with the system architects to develop world-class SOC and IP blocks, which meet power, area and performance targets. . Define, ... configure and integration SoC Subsystems . Contribute to the SoC ...DFT on the blocks . Perform initial synthesis & timing analysis . Assist verification team in unit verification… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior ASIC Design Engineer to join our System ASIC team! NVIDIA has continuously reinvented itself over two decades. Our invention ... to design and implement the world's leading GPU and SoC 's. With the System- ASIC team, you will...be responsible for the RTL design, logic synthesis, and timing analysis of several modules. + Integrate modules into… more
- Tarana Wireless (Milpitas, CA)
- This position will challenge you! The Senior ASIC Engineer will work on complex ASIC designs for our point to multipoint wireless products. + Architecture ... circuits using Verilog + Frontend design development and integration of large ASIC designs including: Integration of Processors, Bus, Memory, and Interface IPs +… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior ASIC Design Engineer. NVIDIA is seeking ASIC Design Engineers to implement the world's leading SoC 's and GPU's. This ... Craft micro-architecture, implement in RTL, and deliver a fully verified, synthesis/ timing clean design. + Collaborate and coordinate with architects, other… more
- NVIDIA (Santa Clara, CA)
- NVIDIA is seeking an outstanding Senior ASIC Design Engineer to design and implement the world's leading SoC 's and GPU's. This position offers the ... fully verified design by working closely with verification engineers. + Deliver a synthesis/ timing clean design while working with the physical design team to ensure… more
- Cisco (San Jose, CA)
- …Your Impact You will be part of the development organization as an ASIC Engineering Technical Leader with primary focus on RTL Design. Key responsibilities: * ... participate in reviews * Implement Verilog RTL to meet timing and performance requirements. * Help define, evolve, and...plus. * Experience with Integrating 3rd party IP's into SoC is desirable * Scripting experience (Python, Perl, TCL,… more
- Amazon (Cupertino, CA)
- …scale and rapid integration of emergent technologies. We're looking for an ASIC Design Eengineer to help us trail-blaze new technologies and architectures, while ... job responsibilities - integrate multiple subsystems into top level SOC , ensure correct clock/reset/functional/DFT signal routing - As a...signal routing - As a key member of the ASIC design team, you will implement and deliver high… more
- Qualcomm (Santa Clara, CA)
- …volume chip production for at least one product cycle is preferred **Keywords** : ASIC ; SOC ; Low Power; Power estimates; Power Intent; Power Implementation; WiFi ... Technology team you will be working on WiFi (802.11x) technology, SOC Design, Low Power micro-architecture, Power Intent/Implementation, power estimates and power… more
- Qualcomm (Santa Clara, CA)
- …at connectivity module level, and chip level modes. You will assist with the timing closure of your designs. You will make regular contributions to the overall ... Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience....Significant contributions in the bring-up of at least one SOC . + Experience on at least two SoC… more
- Broadcom (San Jose, CA)
- … and constraints reports. + Running conformal checks. + Develop and validate timing constraints for intricate SoC designs. + Experience with Synopsys TCM ... you apply.** **Job Description:** Broadcom is looking for a senior level STA engineer. In this highly visible role...highly visible role you will be working on various ASIC products for the next generation of optical and… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior Hardware Design Engineer for our Tegra group! NVIDIA is seeking passionate Senior Hardware Design Engineers to architect, design ... and verify the world's leading SoC 's and GPU's. This position offers the opportunity to...architects, other designers, pre- and post-silicon verification teams, synthesis, timing and back-end teams to accomplish your tasks. What… more
- NVIDIA (Santa Clara, CA)
- We are now hiring for a Senior Logic and Digital Circuit Design Engineer! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in ... as one of the key IPs in many complex SoC . You'll work closely with analog designers and system...define and build constraints for synthesis and drive for timing closure. In addition to RTL design, you'll need… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior Design for Debug (DFD) Architect and Methodology Engineer! NVIDIA is seeking a DFD Architect to implement hardware and software ... solutions to debug world's leading SoC 's and GPU's. This position offers the opportunity to...and/or other silicon visibility tools. + Great understanding of ASIC design flow including RTL design, verification, logic synthesis,… more