- Google (San Diego, CA)
- …technology process nodes. + Experience with ASIC design flows and methodology of static timing analysis . + Effective skills with scripting languages ... Google (https://careers.google.com/benefits/) . + Be responsible for delivering System-on-Chip (SoC) Static Timing Analysis . + Define SoC timing signoff… more
- Qualcomm (San Diego, CA)
- …Snapdragon chips powering billions of mobile devices. The position requires Signoff Timing and spice simulation experience, with CAD development skills to define and ... for accuracy, compute, in close collaboration with Snapdragon Physical Design and Timing teams. Qualcomm is using leading edge internal and EDA technologies in… more
- Google (Sunnyvale, CA)
- … (ie, full chip timing signoff ownership, constraint authoring and verification, full chip static timing analysis and timing ECO creation, timing ... crosstalk. Preferred qualifications: + 10 years of experience in the domain of static timing analysis . + Experience leading one or more aspects of physical… more
- SpaceX (Irvine, CA)
- …Bachelor's degree in electrical engineering, computer engineering or computer science + Experience in static timing analysis and/or timing closure of ... critical deadlines, as needed COMPENSATION & BENEFITS: Pay range: Physical Design STA/ Timing Engineer /Level I: $120,000.00 - $145,000.00/per year Physical Design… more
- Meta (Sunnyvale, CA)
- … timing analysis , SI noise analysis 13. Experience with running Static Timing Analysis for full chip using DMSA 14. Knowledge of front-end and ... experience in front-end implementation from RTL to netlist, including RTL Lint, CDC analysis , timing constraints, synthesis to build efficient System on Chip… more
- NVIDIA (Santa Clara, CA)
- …with 2 years experience in Timing and STA + Hands-on experience in full-chip/sub-chip Static Timing Analysis (STA) and timing convergence, timing ... intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and...inventiveness and intelligence. What you'll be doing: + Drive timing analysis and closure of Nvidia's GPUs,… more
- Cisco (San Jose, CA)
- …with block/full chip SDC development in functional and test modes. * Experience in Static Timing Analysis and prior working experience with STA tools ... of our systems, leveraging the latest technology. We're seeking a talented ASIC engineer with a proven track record in high-performance products, ready to make a… more
- NVIDIA (Santa Clara, CA)
- …next generation of high-performance IPs for CPU, GPU and SOC designs. + Owning static timing analysis and convergence of high-performance designs. + You ... be responsible for all aspects of timing including setting up timing constraints, timing analysis and closure, ECO implementation, and timing … more
- Qualcomm (Santa Clara, CA)
- …setup for various modes/corners and low-power multi-voltage domain crossings, and signoff with static timing analysis . + Collaborate closely with RTL design ... Team is looking for skilled engineers to focus on timing constraints development, power analysis , STA, and timing closure for premium-tier chips.… more
- Cisco (San Jose, CA)
- …with block/full chip SDC development in functional and test modes. * Experience in Static Timing Analysis and prior working experience with STA tools ... from concept to first customer shipments Your Impact You are a diligent Design/SDC Engineer with strong analytical skills and a deep understanding of timing … more
- Qualcomm (San Diego, CA)
- …in die-level IR drop, STA, and power. The engineer should be proficient in static timing analysis using the Synopsys Primetime toolset and should have ... power analysis and optimization, and IR drop analysis and optimization is also helpful. The engineer...signoff **Required Skills and Experience :** ⦁ Expertise in static timing analysis . Hands-on… more
- Meta (Sunnyvale, CA)
- …designs, including physical-aware logic synthesis, floorplan, place and route, clock tree synthesis, static timing analysis , IR drop, EM, and physical ... and IP for data center applications. **Required Skills:** ASIC Engineer , Physical Design Responsibilities: 1. Develop and own physical...H-Tree, and clock power reduction techniques. 21. Knowledge of static timing analysis and concepts,… more
- Broadcom (San Jose, CA)
- …for intricate SoC designs. + Experience with Synopsys TCM tool. + Perform static timing analysis (STA) using industry-standard tools (eg, PrimeTime, ... Description:** Broadcom is looking for a senior level STA engineer . In this highly visible role you will be... timing checks and quality of results (QoR) analysis . + Automate timing analysis … more
- Meta (Sunnyvale, CA)
- …19. 3. Physical Design Execution for Clock Tree Synthesis and Routing optimization 20. 4 Static timing analysis and verification at different PVT corner 21. ... to Job" online on this web page. **Required Skills:** ASIC Engineer , Implementation Responsibilities: 1. Run logic/physical synthesis using advanced optimization… more
- Meta (Sunnyvale, CA)
- …low-power ML Hardware design including physical-aware logic synthesis, floorplan, place and route, static timing analysis , IR Drop, EM, and physical ... area) of the design. **Required Skills:** Silicon Physical Design Engineer Responsibilities: 1. Develop and own physical design implementation...synthesis QoR on low power designs. 14. Knowledge of static timing analysis and concepts,… more
- SpaceX (Sunnyvale, CA)
- …solutions and drive execution + Run, debug, and fix signoff closure issues in static timing analysis (STA), noise, logic equivalency, physical verification, ... SOC/ASIC Physical Design Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where humanity is out exploring the… more
- NVIDIA (Santa Clara, CA)
- …power/clock distribution, chip assembly and P&R, timing closure. + Craft designs for static timing analysis , power and noise analysis and back-end ... We are now looking for a Senior Physical Design Engineer . NVIDIA has continuously reinvented itself over two decades....+ Already a validated strong power user of P&R, Timing analysis , Physical Verification and IR Drop… more
- Capgemini (San Francisco, CA)
- …multiple clock domains and clock gating + Familiarity with timing closure and static timing analysis tools + Experience with scan chain vector generation ... the behavioral model working with Circuit designer. + Develop timing model for the circuit working with layout ...timing model for the circuit working with layout engineer . + This role will provide the ability to… more
- Google (Sunnyvale, CA)
- …design, physical design flows, and methodologies including synthesis, place and route, Static Timing Analysis (STA), formal verification, Change Data ... Capture (CDC), and power analysis . + Experience in IP integration (eg, Phase Lock...unparalleled performance, efficiency, and integration. As a Circuits Design Engineer , Clock Design you will collaborate with the architecture,… more
- Cisco (San Jose, CA)
- …and verifying PCB layout rules and supporting placement feasibility studies * Performing DDR4/DDR5 static timing and signal integrity analysis * Modeling and ... team. What You'll Do: As a Signal Integrity (SI) Engineer , you will be a part of an engineering...SerDes Interfaces * Knowledge of DDR4/DDR5 simulation methodology and timing analysis * Well versed with 3-D… more