- US Tech Solutions (Goleta, CA)
- …AXI, JTAG preferred + Experience in analog and real number modeling preferred **Skills:** + UVM / System Verilog + Design Verification + Ethernet, SPI, ... + The project relates to the design and verification of a custom controller for...simulations + Experience in ethernet and SPI required + UVM / System Verilog experience 5+ years… more
- Cisco (San Jose, CA)
- …combined with 5 years of related experience * Experience in System Verilog / UVM . * Experience with ASIC design and verification processes, debugging, ... with outstanding talent and vast ASIC development expertise in design , DV, DFT, physical design , and post-silicon...micro-architects, front-end designers, and verification engineers. Cisco is a system company, so you can also use the ASIC… more
- Amazon (Sunnyvale, CA)
- …10+ years or more of practical semiconductor design verification experience including System Verilog , UVM , assertions and coverage driven verification. - ... test plans for verification of the full chip or sub- system by working with design engineers and...CPU, NPU, and SOC. - Drive Verification Methodology using System Verilog / C++ based test benches.… more
- Qualcomm (San Diego, CA)
- …and tools. + Creates and maintains verification test benches and environments in System Verilog / UVM + Create and leverage advanced testing frameworks ... experience + Verification skills: Test planning, Scripting, Simulation, problem solving and debug. + System Verilog , UVM , Verilog or VHDL, C/C++ skills… more
- Capgemini (San Francisco, CA)
- …+ Extract modeling specifications from designers + Development of Analog/Mixed-Signal model in System - Verilog + Development of UVM Testbench and developing ... by other groups **Required Skills:** + Good knowledge of System - Verilog RTL coding including state machines, adders,...design for mixed signal control loops and designing Verilog / Verilog - A code to control… more
- Broadcom (Irvine, CA)
- …evolve rapidly at every generation in a very dynamic market using industry proven methodologies using System Verilog and UVM . You can become a member of an ... of a stable team developing silicon products for Ethernet systems in the Cloud? Come join this team creating... UVM , well versed in OOP_** **_T_** **_ools/Languages: System Verilog (TB structures - Class, SVA,… more
- Arrow Electronics (Sunnyvale, CA)
- …**Job Description:** **What candidate will Be Doing:** + At-least 8+ years of experience in System Verilog HVL and C++/C + At-least 8+ year of experience in ... **Position:** Design Verification Engineer (eInfochips Inc) **Job Description:** **Role:...Looking For:** + At-least 8+ years of experience in System Verilog HVL and C++/C + At-least… more
- Meta (Sunnyvale, CA)
- …Requires 5 years of experience in the following: 10. 1. Experience in HDL language ( System Verilog , or Verilog ), and scripting language (TCL, Python, Perl, ... (or foreign degree equivalent) in Computer Science, Engineering, Information Systems , Analytics, Mathematics, Physics, Applied Sciences, or a related...or Shell-scripting) 11. 2. Design Verification in Verification methodologies ( UVM or… more
- Meta (San Diego, CA)
- …of hands-on experience in Verilog , SystemVerilog, C/C++ based verification and UVM methodology. 10. 5+ years experience in IP/sub- system and/or SoC level ... the entire stack, from transistor, through architecture, to firmware, and algorithms.As a Design Verification Engineer at Meta Reality Labs, you will work with a… more
- Meta (San Diego, CA)
- …of hands-on experience in Verilog , SystemVerilog, C/C++ based verification and UVM methodology. 9. 3+ years experience in IP/sub- system and/or SoC level ... entire stack, from transistor, through architecture, to firmware, and algorithms. As a Design Verification Engineer at Meta Reality Labs, you will work with a… more
- Amazon (Sunnyvale, CA)
- …architecture, development, and use of configurable, self-checking testbenches implemented in System Verilog / UVM * Develop constrained-random, metric-driven ... The FPGA verification engineer will work with design and systems teams to define/develop/implement/test/release UVM test environments in order to… more
- Qualcomm (Santa Clara, CA)
- …PASIM simulations + Exposure to perf and power verification. **Skill proficiency** : UVM , system verilog , assertion, C++, python **Technology:** DDR, CACHE, ... this is where you come in as an ASIC Design Verification Engineer The team is responsible for the...team is responsible for the complete verification lifecycle, from system -level concept to tape out and post-silicon support. The… more
- Cisco (San Jose, CA)
- …complex ASICs. You will have a Design Verification background, in-depth experience in System Verilog and UVM methodology, with experience working in C++, ... design and verification flow. * Defining and building UVM /SystemVerilog testbenches from scratch or enhancing existing testbenches with...experience in C/C++ and debugging skills, with experience in System Verilog and UVM methodology… more
- Amazon (Cupertino, CA)
- …field Graduation conferral date between May 2023 and December 2025 Programming experience in System Verilog or UVM Preferred Qualifications Master's or PhD ... Description In Annapurna Labs we are at the forefront of hardware co- design not just in Amazon Web Services (AWS) but across the industry. The work we do is… more
- The Boeing Company (Huntington Beach, CA)
- …Experience with hardware emulators, especially Palladium + Proficiency with hardware verification languages: System Verilog , System Verilog Assertions + ... scoreboards + Drive FPGA-based prototyping and validation depending on program and system requirements and complexity + Validate design through hardware… more
- Qualcomm (Santa Clara, CA)
- …constraint randomization, system Verilog assertions, and performance. + Strong System Verilog / UVM based verification skills, experience with ... large complex IP blocks and subsystems. **Job Responsibilities** + Lead Sub- System & SoC Design verification for Qualcomm WIFI projects + Own end-end low power… more
- Meta (Sunnyvale, CA)
- …to joining Meta 8. Experience with ASIC development cycle. 9. Experience in Verilog , SystemVerilog, C/C++ based verification and UVM methodology. 10. Experience ... the entire stack, from transistor, through architecture, to firmware, and algorithms.As a Design Verification Engineer at Meta Reality Labs, you will work with a… more
- Amazon (Sunnyvale, CA)
- …to ensure functional correctness . Work with the design and communication systems team and participate in system level verification using test benches ... experience - 7+ years in verification preferably in communication systems - 3+ years in UVM , C,... systems - Familiarity with Matlab - Modem design verification experience - System C or… more
- Qualcomm (Santa Clara, CA)
- …for all. The team is responsible for the complete verification lifecycle, from system -level concept to tape out and post-silicon support. The responsibility of the ... position involves comprehensive pre-silicon test planning for system interop verification which includes peripheral IP's such as CXL controller, PCIe controller,… more
- Amazon (Cupertino, CA)
- …- Expertise in various verification languages and tools such as SystemVerilog, UVM , Verilog , and simulation/emulation platforms - Proven track record of ... and Japan, and customers across all industries. Custom SoCs ( System on Chip) live at the heart of AWS...Machine Learning Acceleration team you'll be responsible for the design and optimization of hardware in our data centers… more