- US Tech Solutions (Goleta, CA)
- …and AXI to driven the internal components and send data. **Responsibilities** + As a UVM / SystemVerilog Design Verification Engineer, you will own ... **Job Description:** + The project relates to the design and verification of a custom...with verification methodologies and languages such as UVM and SystemVerilog . + Experience developing and… more
- US Tech Solutions (Goleta, CA)
- …scripting) - must be able to automate test or regression flows **Skills:** + UVM /System Verilog + Design Verification + Ethernet, SPI, AXI, JTAG ... engineer who can work independently and take ownership of verification deliverables within a UVM / SystemVerilog ...tasks. **Experience:** + 5-8 years of experience in Pre-Silicon Design Verification (FPGA or ASIC). + Strong… more
- Google (Mountain View, CA)
- …8 years of experience with verification methodologies and languages such as UVM and SystemVerilog . + Experience developing and maintaining verification ... Senior Design Verification Engineer, Silicon _corporate_fare_ Google...Create and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology ( UVM… more
- Meta (Sunnyvale, CA)
- … verification 8. 2+ years experience in block/IP/sub-system and/or SoC level verification based on SystemVerilog UVM /OVM based methodologies 9. Experience ... from transistors, through architecture, firmware, and algorithms. **Required Skills:** Design Verification Engineer Responsibilities: 1. Define and implement… more
- Meta (Sunnyvale, CA)
- … verification 10. 8+ years experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM /OVM based methodologies 11. Experience ... responsible for the verification closure of a design module or sub-system from test-planning, UVM based test bench development to verification closure.… more
- Meta (Sunnyvale, CA)
- … verification 9. 6+ years of experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM /OVM based methodologies 10. Experience ... responsible for the verification closure of a design module or sub-system from test-planning, UVM based test bench development to verification closure.… more
- Amazon (Sunnyvale, CA)
- …working with design engineers and architects Create and enhance constrained-random verification environments using SystemVerilog and UVM Write tests in ... CE, or CS 10+ years or more of practical semiconductor design verification experience including System Verilog, UVM , assertions and coverage driven … more
- SpaceX (Irvine, CA)
- Design Verification Engineer (Silicon Engineering) Irvine, CA Apply SpaceX was founded under the belief that a future where humanity is out exploring the stars ... the ultimate goal of enabling human life on Mars. DESIGN VERIFICATION ENGINEER (SILICON ENGINEERING) At SpaceX...plans, develop test harnesses and test sequences + Develop SystemVerilog testbench infrastructure (both UVM and non-… more
- BAE Systems (San Diego, CA)
- …in SystemVerilog / UVM , OVM, and/or VHDL + Experience with FPGA/ASIC design and verification tools (Mentor Questa or Cadence) + Proven track record ... and advancing your career. BAE is looking for experienced senior level FPGA Design Verification Engineers who can plan, architect, and develop verification… more
- Meta (Sunnyvale, CA)
- …test cases using industry-standard verification languages and methodologies (eg 4. SystemVerilog , UVM ). 5. Perform simulation and debugging of ASIC designs ... 2. Collaborate with design engineers to understand design intent and identify potential verification challenges....languages (eg Verilog) and verification languages (eg SystemVerilog ) with in UVM (Universal Verification… more
- The Boeing Company (El Segundo, CA)
- …sites. **Position Responsibilities:** + Design and implement an ASIC/FPGA verification environment utilizing UVM & System Verilog. + Develop self-checking ... of the Boeing product line - approximately half our design / verification work is within the Space &...+ Familiarity with defining the architectural framework for ASIC/FPGA verification using SystemVerilog / UVM , including the… more
- Amazon (Sunnyvale, CA)
- … verification , preferably in communication systems - Familiarity with Matlab - Modem design verification experience - System C or Matlab model : development ... . Participate in the validation of ASIC implementations in Verilog/ SystemVerilog . Run formal verification of complex...and communication systems team and participate in system level verification using test benches constructed using UVM ,… more
- Meta (Sunnyvale, CA)
- … verification 10. 8+ years experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM /OVM based methodologies 11. Experience ... responsible for the verification closure of a design module or sub-system from test-planning, UVM based test bench development to verification closure.… more
- Capgemini (Santa Clara, CA)
- …in Electrical Engineering, Computer Engineering or related field + Methodology expertise in UVM and SystemVerilog for SoC verification with the ability ... directed testing, and coverage analysis. + Implement testbenches using UVM , SystemVerilog , C/C , and DPI. +...or Shell scripting + Technical Domains: Ethernet or Mixed-Signal Design Verification + Arm-based SoC Verification… more
- The Boeing Company (Mountain View, CA)
- …architectural definition, and detailed design implementation and functional verification using SystemVerilog with delivery/release of production designs + ... & Weapons Systems has an exciting opportunity for multiple **ASIC and/or FPGA Design and Verification Engineers** (Experienced, Lead, or Senior) to join us… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …or related field 5+ years experience with SystemVerilog , VHDL, Verilog Verification skills such as UVM testbench architecture, development and debug Strong ... R&D, provide in-depth technical assistance to help support advanced verification flows and AI/ML applications to secure design... verification flows and AI/ML applications to secure design wins - Champion the customer needs and work… more
- Teledyne (Milpitas, CA)
- …+ Integrate PCIe IP cores, DMA engines, and custom protocol decoders. + ** Verification & Debug** + Build SystemVerilog / UVM testbenches for block ... teams to deliver industry-leading solutions. **Key Responsibilities** + **RTL Design & Microarchitecture** + Develop synthesizable RTL (Verilog/ SystemVerilog )… more
- NVIDIA (Santa Clara, CA)
- …with assertion-based verification , Semiformal Verification (SFV), Unified Verification Methodology ( UVM ), SystemVerilog checkers and scoreboards. + ... to the design are verifiable + Architect and plan the verification strategy and execution for sub-system features impacting your unit + Support post-silicon… more
- NVIDIA (Santa Clara, CA)
- …server platforms + Working Knowledge of CPU - GPU coherency + Experience with UVM verification environments and scripting with Perl, Python and C/C++ is ... essential. + Be familiar with hierarchical design approach, top-down design , SoC and system level verification . + Zebu emulation experience with SOC/CPU… more
- NVIDIA (Santa Clara, CA)
- …experience. + Individual should be proficient in Verilog and/or VHDL, C/C++ and SystemVerilog . + Experience with UVM verification environments and scripting ... C/C++ is essential. + Be familiar with hierarchical design approach, top-down design , SoC and system level verification . + Candidates will be working on-site… more