- US Tech Solutions (Goleta, CA)
- …and AXI to driven the internal components and send data. **Responsibilities** + As a UVM / SystemVerilog Design Verification Engineer, you will own ... **Job Description:** + The project relates to the design and verification of a custom...with verification methodologies and languages such as UVM and SystemVerilog . + Experience developing and… more
- Meta (Sunnyvale, CA)
- … verification 8. 2+ years experience in block/IP/sub-system and/or SoC level verification based on SystemVerilog UVM /OVM based methodologies 9. Experience ... responsible for the verification closure of a design module or sub-system from test-planning, UVM based test bench development to verification closure.… more
- Meta (Sacramento, CA)
- … verification 10. 8+ years experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM /OVM based methodologies 11. Experience ... responsible for the verification closure of a design module or sub-system from test-planning, UVM based test bench development to verification closure.… more
- Meta (Sunnyvale, CA)
- … verification 9. 6+ years of experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM /OVM based methodologies 10. Experience ... responsible for the verification closure of a design module or sub-system from test-planning, UVM based test bench development to verification closure.… more
- Amazon (Sunnyvale, CA)
- … engineer. Create UVM verification simulation solutions. The FPGA verification engineer will work with FPGA design and systems teams to define ... legacy constraints. The FPGA verification engineer will work with design and systems teams to define/develop/implement/test/release UVM test environments in… more
- Meta (Sunnyvale, CA)
- … verification 10. 8+ years experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM /OVM based methodologies 11. Experience ... responsible for the verification closure of a design module or sub-system from test-planning, UVM based test bench development to verification closure.… more
- Amazon (Sunnyvale, CA)
- …working with design engineers and architects - Create and enhance constrained-random verification environments using SystemVerilog and UVM and write SVA. ... What will you help us create? As a Sr. Design Verification Engineer at Amazon, you will...CS. - 7+ years of hands-on experience in Verilog, SystemVerilog , C/C++ based verification and UVM… more
- Amazon (Sunnyvale, CA)
- …working with design engineers and architects Create and enhance constrained-random verification environments using SystemVerilog and UVM Write tests in ... CE, or CS 10+ years or more of practical semiconductor design verification experience including System Verilog, UVM , assertions and coverage driven … more
- SpaceX (Irvine, CA)
- Design Verification Engineer (Silicon Engineering) Irvine, CA Apply SpaceX was founded under the belief that a future where humanity is out exploring the stars ... the ultimate goal of enabling human life on Mars. DESIGN VERIFICATION ENGINEER (SILICON ENGINEERING) At SpaceX...plans, develop test harnesses and test sequences + Develop SystemVerilog testbench infrastructure (both UVM and non-… more
- Amazon (Cupertino, CA)
- …- Expertise in various verification languages and tools such as SystemVerilog , UVM , Verilog, and simulation/emulation platforms - Proven track record of ... Qualifications - 8+ years of hands-on experience in ASIC/VLSI design verification , with a strong understanding of... verification , with a strong understanding of verification methodologies such as UVM , along with… more
- NVIDIA (Santa Clara, CA)
- We're now looking for a Senior Digital Design Verification Engineer! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 ... join our diverse team today! As a Senior Digital Design Verification Engineer at NVIDIA, you'll verify...models and micro-architecture of the SerDes IPs using advanced verification methodologies such as UVM . + Build… more
- Google (Mountain View, CA)
- …infrastructure IPs, interconnects, and memory subsystems. + Create and enhance constrained-random verification environments using SystemVerilog and UVM . + ... ASIC Design Verification Engineer, Devices and Services...experience with verifying digital logic at RTL level using SystemVerilog or C/C++ Experience creating and using verification… more
- Amazon (Sunnyvale, CA)
- … verification , preferably in communication systems - Familiarity with Matlab - Modem design verification experience - System C or Matlab model : development ... . Participate in the validation of ASIC implementations in Verilog/ SystemVerilog . Run formal verification of complex...and communication systems team and participate in system level verification using test benches constructed using UVM ,… more
- ManpowerGroup (Mountain View, CA)
- …+ Focus on verifying the design of the ASIC/SoC using simulation, formal verification , and emulation. + Utilize tools like SystemVerilog , UVM , VHDL, and ... simulation environments to ensure the chip design meets specifications before fabrication. + Define, document, and...and executing verification plans. + Proficiency in SystemVerilog , UVM , VHDL, and scripting languages such… more
- The Boeing Company (Mountain View, CA)
- …architectural definition, and detailed design implementation and functional verification using SystemVerilog with delivery/release of production designs + ... & Weapons Systems has an exciting opportunity for multiple **ASIC and/or FPGA Design and Verification Engineers** (Experienced, Lead, or Senior) to join us… more
- Google (Mountain View, CA)
- …scenarios. + Create and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology ( UVM ) or formally ... Design Verification Engineer _corporate_fare_ Google _place_ Mountain View, CA, USA **Mid** Experience driving progress, solving problems, and mentoring more… more
- Google (Mountain View, CA)
- …RTL and GLS level using SystemVerilog or C/C++ or Universal Verification Methodology ( UVM ). + Experience with system-level architecture, scripting languages, ... Staff ASIC Design Verification Engineer, Platforms and Devices _corporate_fare_ Google _place_ Mountain View, CA, USA **Advanced** Experience owning outcomes and… more
- NVIDIA (Santa Clara, CA)
- …server platforms + Working Knowledge of CPU - GPU coherency + Experience with UVM verification environments and scripting with Perl, Python and C/C++ is ... essential. + Be familiar with hierarchical design approach, top-down design , SoC and system level verification . + Candidates will be working on-site at our… more
- NVIDIA (Santa Clara, CA)
- …experience. + Individual should be proficient in Verilog and/or VHDL, C/C++ and SystemVerilog . + Experience with UVM verification environments and scripting ... C/C++ is essential. + Be familiar with hierarchical design approach, top-down design , SoC and system level verification . + Candidates will be working on-site… more
- NVIDIA (Santa Clara, CA)
- …in Object Oriented Programming with C++ and/or SystemVerilog + Exposure to design and verification tools (VCS or equivalent simulation tools, debug tools ... NVIDIA is seeking an outstanding Senior ASIC Verification Engineer to verify the design ...like Debussy, GDB), and methodologies ( UVM or equivalent) + Your work displays a passion… more