- US Tech Solutions (Goleta, CA)
- …and AXI to driven the internal components and send data. **Responsibilities** + As a UVM / SystemVerilog Design Verification Engineer, you will own ... **Job Description:** + The project relates to the design and verification of a custom...with verification methodologies and languages such as UVM and SystemVerilog . + Experience developing and… more
- Meta (Sunnyvale, CA)
- …ASIC development cycles 9. 3+ years experience in block/IP/sub-system and/or SoC level verification based on SystemVerilog UVM /OVM based methodologies 10. ... responsible for the verification closure of a design module or sub-system from test-planning, UVM ...to joining Meta. 7. 3+ years hands-on experience in SystemVerilog / UVM methodology or C/C++ based verification… more
- Meta (Sunnyvale, CA)
- …development cycles. 10. 5+ years of experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM /OVM based methodologies. 11. ... responsible for the verification closure of a design module or sub-system from test-planning, UVM ...practical experience. 8. 5+ years of hands-on experience in SystemVerilog / UVM methodology and/or C/C++ based verification… more
- Meta (Sunnyvale, CA)
- … verification . 10. 10+ years experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM /OVM based methodologies. 11. Experience ... responsible for the verification closure of a design module or sub-system from test-planning, UVM based test bench development to verification closure.… more
- Meta (Sunnyvale, CA)
- … UVM methodology. 9. 3+ years experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM /OVM based methodologies. 10. Experience ... transistor, through architecture, to firmware, and algorithms. As a Design Verification Engineer at Meta Reality Labs,...13. Experience in development of UVM based verification environments from scratch. 14. Experience with Design… more
- Meta (San Diego, CA)
- … UVM methodology. 9. 3+ years experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM /OVM based methodologies. 10. Experience ... from transistor, through architecture, to firmware, and algorithms.As a Design Verification Engineer at Meta Reality Labs,...14. Experience in development of UVM based verification environments from scratch. 15. Experience with Design… more
- Northrop Grumman (Mcclellan, CA)
- …SystemVerilog ). Experience with SystemVerilog Assertions (SVA) and Universal Verification Methodology ( UVM ) is required. Successful candidates will have ... + Experience with SystemVerilog Assertions (SVA) + Knowledge of Universal Verification Methodology ( UVM ) + Experience with scripting languages (Bash, Perl,… more
- Qualcomm (Santa Clara, CA)
- …planning for digital power IP's, its testbench development using the advanced verification methodology such as SystemVerilog - UVM , coverage development, ... related field + 10+ years of experience with ASIC design and verification tools, techniques, and methodology...and methodology + 12+ years of experience with digital design concepts and RTL languages such as SystemVerilog… more
- Google (Sunnyvale, CA)
- …logic at RTL using SystemVerilog for ASICs. + Experience in memory subsystem design verification . + Experience in Power aware verification , Gate level ... engineers to identify important verification scenarios. + Create a constrained-random verification environment using SystemVerilog and UVM . + Identify… more
- Meta (Sunnyvale, CA)
- …verification . 10. 10+ years of experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM /OVM based methodologies. 11. ... entire stack, through algorithms to architecture, transistors to firmware. As a Design Verification Engineer at Meta's Reality Labs, you will work with a… more
- Meta (Sunnyvale, CA)
- …Minimum Qualifications: 7. Experience with ASIC development cycle. 8. Experience in Verilog, SystemVerilog , C/C++ based verification and UVM methodology. 9. ... the entire stack, from transistor, through architecture, to firmware, and algorithms.As a Design Verification Engineer at Meta Reality Labs, you will work with… more
- Qualcomm (San Diego, CA)
- … design team. + Architect and develop the testbench using advanced verification methodology such as SystemVerilog / UVM , Analog/mixed signal simulation, Low ... Group, Engineering Group > ASICS Engineering **General Summary:** Join Qualcomm's design verification team in verifying the high-speed mixed-signal IP… more
- Siemens (Fremont, CA)
- …800G, 1.6T, UEC and beyond . + Develop scalable VIP frameworks leveraging UVM (Universal Verification Methodology), SystemVerilog , and formal verification ... expertise in Ethernet technology and a strong focus on design verification . In this role, you...and networking protocols . + Strong hands-on experience with SystemVerilog , UVM , and scripting languages (Python, TCL,… more
- Google (Mountain View, CA)
- …scenarios. + Create and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology ( UVM ) or formally ... digital Intellectual Property (IP) and subsystems. + Experience in Design Verification (DV) Testbenches/Environments. Preferred qualifications: + Master's… more
- Amazon (Sunnyvale, CA)
- …or CS - 10+ years or more of practical semiconductor design verification experience including System Verilog, UVM , assertions and coverage driven ... generation of Echo devices is looking for a Senior Design Verification Engineer to continue to innovate... engineers and architects - Create and enhance constrained-random verification environments using SystemVerilog and UVM… more
- Amazon (Sunnyvale, CA)
- …or CS - 7 years or more of practical semiconductor design verification experience including System Verilog, UVM , assertions and coverage driven ... Description As a Senior Design Verification (DV) Engineer, you will... engineers and architects - Create and enhance constrained-random verification environments using SystemVerilog and UVM… more
- SpaceX (Irvine, CA)
- Design Verification Engineer (Silicon Engineering) Irvine, CA Apply SpaceX was founded under the belief that a future where humanity is out exploring the stars ... the ultimate goal of enabling human life on Mars. DESIGN VERIFICATION ENGINEER (SILICON ENGINEERING) At SpaceX...plans, develop test harnesses and test sequences + Develop SystemVerilog testbench infrastructure (both UVM and non-… more
- BAE Systems (San Diego, CA)
- …in SystemVerilog / UVM , OVM, and/or VHDL + Experience with FPGA/ASIC design and verification tools (Mentor Questa or Cadence) + Proven track record ... and advancing your career. BAE is looking for experienced senior level FPGA Design Verification Engineers who can plan, architect, and develop verification… more
- Qualcomm (Santa Clara, CA)
- …planning for digital power IP's, its testbench development using the advanced verification methodology such as SystemVerilog - UVM , coverage development, ... this is where you come in as an ASIC Design Verification Engineer The team is responsible...flow and methodology. Involve in developing automation to improve verification efficiency. **Qualifications:** + DV experience using uvm… more
- Amazon (Cupertino, CA)
- …- Expertise in various verification languages and tools such as SystemVerilog , UVM , Verilog, and simulation/emulation platforms - Proven track record of ... Qualifications - 8+ years of hands-on experience in ASIC/VLSI design verification , with a strong understanding of... verification , with a strong understanding of verification methodologies such as UVM , along with… more