- Qualcomm (San Diego, CA)
- …for the Snapdragon chips powering billions of mobile devices. The position requires Signoff Timing and spice simulation experience, with CAD development skills ... of STA features and Timing concepts. + 2-6 years of experience in Signoff Timing of SoCs at either top-level or block-level. * 2-6 years of experience with… more
- Qualcomm (San Diego, CA)
- …for various modes/corners and low-power multi-voltage domain crossings, and signoff with static timing analysis . + Collaborate closely with RTL design ... Team is looking for skilled engineers to focus on timing constraints development, power analysis , STA, and timing closure for premium-tier chips.… more
- Google (San Diego, CA)
- …. + Be responsible for delivering System-on-Chip (SoC) Static Timing Analysis . + Define SoC timing signoff process corners, derates, uncertainties ... + Experience with ASIC design flows and methodology of static timing analysis . + Experience...full chip timing constraint creation and validation, timing signoff checklist criteria, perform full chip… more
- Qualcomm (San Diego, CA)
- …in die-level IR drop, STA, and power. The engineer should be proficient in static timing analysis using the Synopsys Primetime toolset and should ... Develop strategies for 3DIC, datacenter and chiplet designs PDN analysis and signoff **Required Skills and Experience...Skills and Experience :** + Strong conceptual understanding in static timing analysis . Hands-on experience… more
- Qualcomm (San Diego, CA)
- …- Synopsys Fusion Compiler, ICC2 and Cadence Genus/Innovus + Must have good knowledge of static timing analysis , reliability and power analysis + Strong ... + Hands on experience with Synthesis, DFT, Place and Route, Timing and Reliability Signoff + Hands on experience working with very complex designs that… more
- Qualcomm (San Diego, CA)
- …- Synopsys Fusion Compiler, ICC2 and Cadence Genus/Innovus + Must have good knowledge of static timing analysis , reliability and power analysis + Strong ... closure + Hands on experience with Synthesis, DFT, Place and Route, Timing and Reliability Signoff + Hands on experience working with very complex designs that… more
- Qualcomm (San Diego, CA)
- …> GPU ASICS Engineering **General Summary:** **Preferred Qualifications:** + Experience in static timing analysis , constraints and other physical ... using TCL and preferably Perl/Python as well. **Responsibilities** **:** + Timing analysis , validation and debug across multi-mode, multi-voltage domain… more