- Qualcomm (Austin, TX)
- …SoC Implementation Team is looking for skilled engineers to focus on timing constraints development, power analysis, STA , and timing closure for ... This is an excellent opportunity to join the Snapdragon implementation team, which is responsible for SoCs in sub-3nm...and low-power multi-voltage domain crossings, and signoff with static timing analysis. + Collaborate closely with RTL design… more
- Qualcomm (Austin, TX)
- …you will work with microarchitecture and RTL design team to develop timing constraints, drive implementation of the designs to meet aggressive power, area ... Design Timing Engineer,... automation using TCL/Perl/Python. + Familiar with digital flow design implementation RTL to GDS : ICC, Innovous… more
- Cadence Design Systems, Inc. (Austin, TX)
- …Backend Digital Design Implementation and Signoff including Place and Route, Design Closure, and timing /power signoff + Guide customers on how to best ... nanometer design , unlock unique expertise in digital design implementation , and level up your communication,...STA , Prime Time, Tempus, ETS* Strong fundamentals in Timing / timing closure. We're doing work… more
- Cadence Design Systems, Inc. (Austin, TX)
- …Joules) + Logic and low power verification, UPF expertise (Conformal, Formality) + Static timing ( STA ) and power analysis (Tempus, Primetime, Voltus, PTPX) + ... is a highly motivated applications engineer, who leverages technical skills and design knowledge to showcase Cadence products, maximizing product sales. This role is… more
- Qualcomm (Austin, TX)
- …Experience of synthesis, physical design (Genus, Innovus or FusionCompiler) and STA timing closure. + Knowledge of semiconductor device physics and behavior; ... the IP specification definition, RTL design , architecture and circuit design , physical implementation , verification and sign offs. Candidates with coding… more
- Samsung Electronics Co., Ltd. (Austin, TX)
- …verify the functionality and correctness of the design . + You collaborate with implementation to achieve your timing and area. + You produce quality RTL on ... be interacting with the system architects, verification, performance/power and design implementation teams. You will be owning...power optimization and also work on logic debug and timing closure of the design . Solid engineer… more