• ASIC IP Design Manager

    Meta (Sunnyvale, CA)
    …role, you will lead the development of cutting-edge hardware accelerator IPs. **Required Skills:** ASIC IP Design Manager , Reality Labs Responsibilities: ... we invite you to join our team as an ASIC Design Manager . In this...Execution: Drive RTL design planning and execution, design methodology development, IP design ,… more
    Meta (06/04/25)
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  • Silicon IP Technical Program Manager

    Meta (Sunnyvale, CA)
    …technical sessions to track and follow up on issues. **Required Skills:** Silicon IP Technical Program Manager Responsibilities: 1. Serve as the primary point ... Qualifications:** Minimum Qualifications: 12. 10+ years of experience in silicon/ ASIC /firmware/ IP program management. 13. Experience dealing with ambiguity… more
    Meta (06/04/25)
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  • Silicon Verification Manager - AI…

    Meta (Menlo Park, CA)
    …experience 11. Knowledge with assertions (SVA) or others 12. Knowledge of digital ASIC design flows, project management and milestones 13. Knowledge of ... at the entire stack, from transistors, through architecture, firmware, and algorithms. As a Design Verification Manager at Meta Reality Labs, you will work with… more
    Meta (05/08/25)
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  • Field Applications Engineering Manager

    quadric.io, Inc (Burlingame, CA)
    …in compiler strategies for data parallel processors such as GPUs, DSPs and ASIC design flows * Knowledge of end-to-end toolchain, including compilers, linkers ... Field Applications Manager (Worldwide) Location: Burlingame, CA Description If making...using our Chimera GPNPU (general purpose neural processor unit) IP for a wide range of products -- from… more
    quadric.io, Inc (06/09/25)
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  • Silicon Technical Program Manager

    Meta (Sunnyvale, CA)
    …**Minimum Qualifications:** Minimum Qualifications: 10. 7+ years of experience in silicon/ ASIC / IP program management. 11. Experience dealing with ambiguity with ... our industry-leading virtual reality systems forward. As a Silicon Technical Program Manager for MR New Technology Platforms, you will lead multidisciplinary teams… more
    Meta (05/30/25)
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  • STA Engineer (eInfochips Inc)

    Arrow Electronics (San Jose, CA)
    …timing** in multiple timing modes. + Option to also do block level RTL design or block or top-level IP integration. + Helping develop efficient methodology ... **What You'll Be Doing:** + Being a member of design team who oversees **fullchip SDCs** and works with...in Electrical or Computer Engineering with 7+ years of ASIC or related experience or Master's Degree in Electrical… more
    Arrow Electronics (06/06/25)
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