- Google (Sunnyvale, CA)
- …measuring chip power consumption. + Develop design improvements to increase power efficiency . + Collaborate with cross-functional teams in defining power ... using EDA tools such as PTPX, PowerArtist, or PrimePower. + Experience driving power - efficiency improvement in chip designs. + Experience with pre-silicon vs… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior ASIC Power Engineer ! NVIDIA is seeking extraordinary power engineers to design hardware accelerators and processors on ... to extend the state of the art performance and efficiency + You are expected to understand the design...are expected to understand the design and implementation, develop power metrics and drive power reductions +… more
- NVIDIA (Santa Clara, CA)
- We are now looking for an ASIC Design Efficiency Engineer ! NVIDIA is seeking extraordinary methodology engineers to design hardware accelerators and ... and system designs to extend the state of the art performance and efficiency . + Understand the design and implementation, develop methodology and infrastructure to… more
- Google (Sunnyvale, CA)
- …will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency , and integration. As a Design Engineer , you will play ... + Experience with industry-standard EDA tools for simulation, synthesis, and power analysis. Preferred qualifications: + Master's degree or PhD in Electrical… more
- Qualcomm (Santa Clara, CA)
- …of the position involves comprehensive pre-silicon test planning for digital power IP's, its testbench development using the advanced verification methodology such ... model development and formal verification (property checking). Learn and deploy power -aware UPF verification flow and methodology. Involve in developing automation… more
- NVIDIA (Santa Clara, CA)
- NVIDIA is seeking an outstanding Senior ASIC Design Engineer to design and implement the world's leading SoC's and GPU's. This position offers the opportunity to ... Computer Architecture and Digital Systems design. + A deep understanding of ASIC design flow including RTL design, verification, logic synthesis, timing analysis,… more
- Google (Sunnyvale, CA)
- …and its integration within AI/ML-driven systems. As an Application-Specific Integrated Circuit ( ASIC ) Physical Design Engineer on the Chip Implementation team, ... Experience with EMIR parameters, analysis, violation mitigation and tradeoffs related to power grid design and augmentation. + Experience in advanced process nodes… more
- Google (Mountain View, CA)
- …like Python or Perl. + Experience with ARM-based SoCs, interconnects and ASIC methodology. Preferred qualifications: + Master's degree or PhD in Electrical ... industry experience with IP design. + Experience with methodologies for low power estimation, timing closure, synthesis. + Experience with methodologies for RTL… more
- Google (Sunnyvale, CA)
- …ASICs. + Experience in memory subsystem design verification. + Experience in Power aware verification, Gate level simulations, and Post silicon bring-up. + ... Familiarity with ASIC standard interfaces and memory system architecture. In this...team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to… more
- NVIDIA (Santa Clara, CA)
- …power data, and driving ASIC teams to improve their units' power efficiency ; and is responsible for researching, developing, and deploying methodologies ... We are now looking for a Senior Power Architecture and Optimization Engineer ! NVIDIA... power analysis tools, to help improve product power efficiency . + Develop and share best… more
- NVIDIA (Santa Clara, CA)
- …power data and driving ASIC teams to improve their units' power efficiency ; and is responsible for researching, developing, and deploying methodologies to ... We are looking for a Senior Emulation Power Engineer ! NVIDIA prides in having...concepts of energy consumption, estimation, data movement and low power design. + Familiarity with Verilog and ASIC… more
- NVIDIA (Santa Clara, CA)
- …pre-silicon gate-level and RTL power analysis tools, to help improve product power efficiency . + Develop and share best practices for performing pre-silicon ... We are now looking for a Power Architecture and Optimization Engineer -...concepts of energy consumption, estimation, data movement and low power design. + Familiarity with Verilog and ASIC… more
- Qualcomm (Santa Clara, CA)
- …are highly optimized for the needs of the server product. **Position: Server Chipset Power Engineer ** We are seeking a highly experienced Server Chipset Power ... innovative solutions that push the limits of performance, energy efficiency , and scalability. Our focus is on developing server-class... and silicon/system limits + Strong fundamentals in digital ASIC design and power of CMOS circuits… more
- NVIDIA (Santa Clara, CA)
- …a trailblazer at the forefront of graphics and artificial intelligence performance, efficiency , and innovation. From our roots as a groundbreaking graphics company, ... industries. NVIDIA Silicon Solutions Group is seeking a versatile engineer to be part of the HW ArchDev team....Build roadmaps of system level features to address low power , low noise, perf/watt efficient product needs by doing… more
- Qualcomm (Santa Clara, CA)
- …**General Summary:** As a Design Verification Lead, you will lead a team of ASIC design verification engineers to verify IP and Subsystems that be integrated in a ... validation and design teams to verify IP that meets power , performance and area goals for Qualcomm Wireless and...debugs + Build, manage and mentor a team of ASIC DV engineers + Explore innovative DV methodologies (formal,… more
- Palo Alto Networks (Santa Clara, CA)
- …integrity analysis of ASIC and multi-chip-module designs + Model and analyze power delivery networks for ASIC /package/module and PCB + Create SI test plan ... Experience** + Strong background in hands-on design and validation of high-speed PCB and ASIC package development + Power integrity design and analysis and well… more
- Qualcomm (Santa Clara, CA)
- …is the Invention Age - and this is where you come in as an ASIC Design Verification Engineer The team is responsible for the complete verification lifecycle, ... of the position involves comprehensive pre-silicon test planning for digital power IP's, its testbench development using the advanced verification methodology such… more
- Meta (Sunnyvale, CA)
- …Virtual Reality (VR) and Augmented Reality (AR). The compute performance and power efficiency requirements of Virtual and Augmented Reality require custom ... **Summary:** Meta's mission is to give people the power to build community and bring the world...learning accelerators and state-of-the-art SoCs. **Required Skills:** Digital Design Engineer Responsibilities: 1. Contribute to ASIC digital… more
- Google (Sunnyvale, CA)
- …will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency , and integration. As a SoC Design Engineer , you will ... Experience with industry-standard EDA tools for simulation, synthesis and power analysis. Preferred qualifications: + Master's degree or PhD...on computer architecture. + 10 years of experience in ASIC design with 3 years of experience working on… more
- Meta (Menlo Park, CA)
- **Summary:** Meta is seeking a Hardware Systems Engineer to join our Release to Production (RTP) team working on new NPI hardware. Our servers and data centers are ... software and hardware technologies for AI at datacenter scale. Hardware Systems Engineer in RTP work closely with HW/SW co-design teams, hardware designers,… more