• CMOS Device and Memory

    Google (Mountain View, CA)
    …embedded SRAM design (cell and macro) and characterization. + Experience in CMOS technology and device characterization, process integration and SPICE ... + Experience in product-level testing in Static Random Access Memory (SRAM) including yield and parametric evaluation. + Excellent...(PDPPA) team to evaluate PPA accounting both logic and memory at IP level. + Work with the IP… more
    Google (05/30/25)
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  • Senior Mixed Signal Design Engineer

    NVIDIA (Santa Clara, CA)
    We are looking for a Senior Mixed-Signal/Analog/IO Circuit Design Engineer - someone who is excited to join a rapidly growing team of creative circuit design ... you'll be doing: + Mixed-Signal/Analog circuit design for High-Speed Memory I/O Interfaces + Solve challenges of circuit designs...+ Solve challenges of circuit designs in the latest CMOS FinFET processes + Take designs through productization and… more
    NVIDIA (04/13/25)
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  • Senior Timing and VF Methodology Engineer

    NVIDIA (Santa Clara, CA)
    …intelligence. We are seeking an innovative senior timing and VF Methodology engineer to develop pioneering timing sign-off strategies for next-generation GPUs and ... 3+ years' experience in ASIC Design and Timing. + Knowledge of device physics, STA methodology. + Good understanding of mathematics/physics fundamentals of… more
    NVIDIA (05/22/25)
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