- Qualcomm (Santa Clara, CA)
- …drive CPU timing closure for Oryon CPU Cores. As a CPU Physical Design Timing Engineer, you will work with microarchitecture and RTL ... design team to develop timing constraints, drive...with STA native tools and also useful in enabling CPU timing infrastructure and methodology impacting multiple… more
- Qualcomm (Santa Clara, CA)
- …to create designs that push the envelope on performance, energy efficiency and scalability. As CPU Physical Design CAD engineer, you will build and support ... and resolve project-specific issues + Work closely with worldwide CPU physical design teams, and...nodes (5nm or lower) + Solid understanding of digital design , timing analysis and physical … more
- Qualcomm (Santa Clara, CA)
- … operations for all Qualcomm Business Units. Minimum Skill/Experience: + 2-10 yrs experience in Physical Design and timing signoff for high speed cores. + ... Engineer, you will lead innovative Central Processing Unit ( CPU ) design efforts that have a critical...Should have good exposure to high frequency design convergence for physical design … more
- Qualcomm (Santa Clara, CA)
- …Work with multi-functional engineering team to implement and validate physical design on the aspects of timing , area, reliability, testability and power. ... Technologies, Inc. **Job Area:** Engineering Group, Engineering Group > CPU Engineering **General Summary:** We are hiring a talented...simulators and waveform debugging tools. * Knowledge of logic design principles along with timing and power… more
- Qualcomm (Santa Clara, CA)
- …synthesis, place & route and tape out flows. Roles and Responsibilities + Perform CPU physical design tasks, including floorplanning, Bump/RDL planning, IP ... and physical design teams to design , floorplan and integrate the CPU designs...+ Proficiency in synthesis, place and route, and signoff timing /power analysis. + Expertise in block-level implementation as well… more
- Qualcomm (Santa Clara, CA)
- …Work with multi-functional engineering team to implement and validate physical design on the aspects of timing , area, reliability, testability and po ... targeted for high performance, low power devices. As a CPU Micro-architecture and RTL Design Engineer, you...+ RTL ownership. Development, assessment and refinement of RTL design to target power, performance, area and timing… more
- NVIDIA (Santa Clara, CA)
- …need to see: + BS or MS (or equivalent experience) + 6+ years of CPU design implementation experience + Deep understanding of logic optimization techniques and ... expertise to improve PPA (power, performance and area) on CPU designs by collaborating with logic designers, physical...from Synopsys (DC/FC), Cadence (Genus/Innovus) + Strong understanding of physical design implementation eg: physical … more
- NVIDIA (Santa Clara, CA)
- …skills and ability to collaborate with cross-functional teams. + Strong understanding of timing and physical design fundamentals Ways to stand out ... CPU , GPU and SOC designs. + Owning static timing analysis and convergence of high-performance designs. + You...(or equivalent experience) with 3+ years' experience in ASIC Design and Timing + Hands-on experience in… more
- Amazon (Sunnyvale, CA)
- …device physics, custom/semi-custom implementation techniques - Experience solving physical design challenges across various technologies such as CPU , DDR, ... generation of Echo devices is looking for a Sr. Physical Design Engineer to continue to innovate...pin planning, place and route, power/clock distribution, congestion analysis, timing closure, IR drop analysis, physical verification,… more
- NVIDIA (Santa Clara, CA)
- …and intelligence. What you will be doing: + Developing innovative physical design methodologies for implementation of GPU, CPU and SOCs, with emphasis on ... PPA (Power, Performance, Area) and runtime improvement of the physical design flow on advanced technology nodes...timing and RC correlation + Good understanding of design rules in advanced nodes and their impact on… more
- Broadcom (San Jose, CA)
- …knowledge of IC technology, ASIC design flows, EDA tools and Physical design considerations. 3). Thorough knowledge of high-speed Ethernet networking and ... and working on initial floor plan. 4). Develop Verilog RTL. logic synthesis, physical implementation constraints, static timing analysis. 5). Work directly with… more
- Broadcom (San Jose, CA)
- …strong technical hands-on competency in using leading edge physical design EDA tools in projects. + In-depth CPU /DSP architecture/algorithm working ... System-On-Chip ASICs. Key competencies required are: + Working experience in (digital) physical design implementation of large scale ASICs (Multi-100 million… more
- SanDisk (Milpitas, CA)
- …creating high-performance semiconductor solutions. ESSENTIAL DUTIES AND RESPONSIBILITIES: + Design and implement complex ASIC architectures using advanced RTL ... techniques + Develop and optimize SoC subsystems, including CPU complex, DDR, Host, Flash, Debug, Clocks, resets, and...of ASIC designs into larger systems + Conduct thorough design reviews and provide technical leadership to junior engineers… more