- Google (Sunnyvale, CA)
- …of static timing analysis. + Experience leading one or more aspects of physical design or physical design flow/methodology, to successful tape-outs ... field, or equivalent practical experience. + 7 years of experience in static timing (ie, full chip timing signoff ownership, constraint authoring and verification,… more
- Google (Sunnyvale, CA)
- …of static timing analysis. + Experience leading one or more aspects of physical design or physical design flow/methodology, to successful tape-outs ... equivalent practical experience. + 3 years of experience in static timing (eg, full chip timing signoff ownership, constraint...and shipping silicon. + Experience in extraction of design parameters, QoR metrics, and analyzing data trends. +… more
- Meta (Sunnyvale, CA)
- …Emulation Engineers in supporting them with the handoff tasks. Interact with Physical Design Engineers and provide them with timing/congestion feedback. ... (SoC) and IP for data center applications. **Required Skills:** ASIC Implementation Engineer - Static Verification Responsibilities: 1. Perform Flat and… more
- Meta (Sunnyvale, CA)
- …System on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Engineer , Physical Design Responsibilities: 1. Develop and own ... **Summary:** Meta is hiring ASIC Physical Design Engineers within our Infrastructure...logic synthesis, floorplan, place and route, clock tree synthesis, static timing analysis, IR drop, EM, and physical… more
- Meta (Sunnyvale, CA)
- …PPA (Power, Performance, and area) of the design . **Required Skills:** Silicon Physical Design Engineer Responsibilities: 1. Develop and own physical ... implementation of multi-hierarchy low-power ML Hardware design including physical -aware logic synthesis, floorplan, place and route, static timing analysis,… more
- SpaceX (Sunnyvale, CA)
- SOC/ASIC Physical Design Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where humanity is out exploring ... ultimate goal of enabling human life on Mars. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING)...+ Run, debug, and fix signoff closure issues in static timing analysis (STA), noise, logic equivalency, physical… more
- Google (Sunnyvale, CA)
- …its integration within AI/ML-driven systems. As an Application-Specific Integrated Circuit (ASIC) Physical Design Engineer on the Chip Implementation team, ... Google (https://careers.google.com/benefits/) . + Work on physical design including place and route, EMIR, static ... design including place and route, EMIR, static timing, and physical verification. + Go… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior Physical Design Engineer . NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 ... you'll be doing: + Responsible for all aspects of physical design and implementation of GPU and...assembly and P&R, timing closure. + Craft designs for static timing analysis, power and noise analysis and back-end… more
- Google (Sunnyvale, CA)
- …a related field, or equivalent practical experience. + 7 years of physical design experience with industry-standard tools, languages, and methodologies relevant ... silicon interposer design and advanced packaging technologies. + Experience crafting physical design automation flows. In this role, you'll work to shape… more
- NVIDIA (Santa Clara, CA)
- …timing paths through ECOs including crosstalk and noise analysis. + Expertise in physical design and optimization eg, placement, routing, cell sizing, buffering, ... We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If...in Synthesis and Timing + Hands-on experience in full-chip/sub-chip Static Timing Analysis (STA), timing constraints generation and management,… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a motivated Senior Circuit Design Engineer to join our dynamic and growing team. If you are looking for a challenging and exciting role in ... analysis on the design . + Drive the design and physical implementation of digital and/or...Hands on experience running Spice simulations, EM/IR analysis, and static timing analysis/closure + Experience with spice simulation for… more
- NVIDIA (Santa Clara, CA)
- We are now hiring for a Logic and Digital Circuit Design Engineer ! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 ... teams to define a unified interface + Work with Physical design engineers, floor planning, define timing...DFE, CTLE, CDR, and offset cancellation + Experience with static timing tools (nanotime, primetime) and formal verification tools… more
- NVIDIA (Santa Clara, CA)
- We are now hiring for a Senior Library Design Engineer ! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the ... Advanced Technologies Group is looking to hire a Library Design Engineer in our group. Do you...an in-depth understanding of circuits, simulation, library characterization and static timing analysis? Enjoy working on the cutting edge… more
- Broadcom (San Jose, CA)
- …knowledge of IC technology, ASIC design flows, EDA tools and Physical design considerations. 3). Thorough knowledge of high-speed Ethernet networking and ... and working on initial floor plan. 4). Develop Verilog RTL. logic synthesis, physical implementation constraints, static timing analysis. 5). Work directly with… more
- Broadcom (San Jose, CA)
- …involve in engineering implementation spec writing from marketing/system requirements, RTL design and verification, synthesis, static timing analysis. You will ... team. You will work closely with marketing, architecture, firmware, physical and layout teams on full product development cycle...either be responsible for block and/or chip level design and integration. Job Requirements BSEE/MSEE. Minimum 8 years… more
- Qualcomm (Santa Clara, CA)
- …crossings, and signoff with static timing analysis. + Collaborate closely with RTL design and physical design teams to identify timing requirements and ... Description: Principal Duties and Responsibilities** + Develop constraints for physical power-aware synthesis, setup for various modes/corners and low-power… more
- Microsoft Corporation (Santa Clara, CA)
- …+ Review and provide feedback on verification plans and methodology. + Collaborate with Physical design teams to ensure design meets timing and area ... Systems & Infrastructure group is seeking a Senior Silicon Engineer . You will join our front-end silicon team and...equivalent experience. + 5+ years of experience with RTL design and/or architecture experience. + 5+ years of experience… more
- Arrow Electronics (San Jose, CA)
- …a member of design team who oversees **fullchip SDCs** and works with physical design and DFT teams to close **fullchip timing** in multiple timing modes. ... **Position:** STA Engineer (eInfochips Inc) **Job Description:** **Position: STA ...+ Option to also do block level RTL design or block or top-level IP integration. + Helping… more
- Qualcomm (Santa Clara, CA)
- …flows, and resolve project-specific issues + Work closely with worldwide CPU physical design teams, and provide methodology guidance and tools/flows support. ... Responsibilities:** * Leverages advanced knowledge of computer architecture, micro-architecture, logic design , circuits, and/or physical design to develop… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …Innovus product. Innovus is a complete digital implementation product that encompasses physical design and logic synthesis. The product breadth means we ... Systems is looking for a highly motivated software engineer to work as a member of the R&D...supporting the Innovus product. This specific role will require physical design and synthesis domain knowledge on… more