- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. NVIDIA is looking for best-in-class Senior Physical Design Methodology Engineer (s) - PPA Fusion ... technology-focused company. What you will be doing: + Developing Efficient physical design methodologies for implementation of graphics processors and SOCs. +… more
- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. NVIDIA is looking for best-in-class Senior Physical Design Methodology Engineer (s) to join our ... impact in a technology-focused company. What you will be doing: + Developing physical design methodologies for implementation of graphics processors and SOCs. +… more
- Amazon (Cupertino, CA)
- …of machine learning and AI services for our customers' businesses. We are seeking experienced Physical Design Engineer to build the next generation of our ... today. Key job responsibilities - You will create and support innovative physical design methodology and CAD flows. - Develop cloud infrastructure to… more
- NVIDIA (Santa Clara, CA)
- …human inventiveness and intelligence. What you will be doing: + Developing innovative physical design methodologies for implementation of GPU, CPU and SOCs, with ... PPA (Power, Performance, Area) and runtime improvement of the physical design flow on advanced technology nodes...with internal and external partners to drive tool and methodology improvements to deliver best-in-class PPA solutions across all… more
- quadric.io, Inc (Burlingame, CA)
- …Happiness What We Expect: Initiative, Collaboration, Completion Role As a member of our physical design methodology team you will be tasked with developing ... physical design methodologies and automation scripts for multiple design configurations across multiple process nodes. Responsibilities + Develop Quadric… more
- NVIDIA (Santa Clara, CA)
- …devices for high-speed optical interconnect and sensing applications. + Developing physical design methodologies for implementation of graphics processors and ... driving cars. Come join us in our mission to Engineer the next generation of best-in-class products. Our teams...and creative solutions to the state of the art physical design problems that are needed for… more
- NVIDIA (Santa Clara, CA)
- …intelligence. We are seeking an innovative senior timing signoff and constraint methodology engineer to develop pioneering timing sign-off strategies for ... next-generation GPUs and SoCs. In this role, you'll develop methodology and flows to validate timing constraints from RTL...clock domains across hierarchical boundaries). + Collaborate with RTL, physical design , and verification teams to drive… more
- NVIDIA (Santa Clara, CA)
- We are looking for a Senior CPU Implementation Methodology Engineer to join our VLSI team! If you are looking for a challenging and exciting role and you are a ... from Synopsys (DC/FC), Cadence (Genus/Innovus) + Strong understanding of physical design implementation eg: physical ...out from the crowd: + Prior CPU experience in physical implementation methodology + Proficiency in Perl,… more
- NVIDIA (Santa Clara, CA)
- …databases, but it mostly requires a strong VLSI background in static timing, physical design , and related optimization techniques. Collaborating with design ... times per day. We are seeking a Senior CAD Engineer excited to innovate in strategies for complex timing,...optimization opportunities, to developing solutions and working directly inside design teams to facilitate deployment. What we need to… more
- Qualcomm (Santa Clara, CA)
- …create designs that push the envelope on performance, energy efficiency and scalability. As CPU Physical Design CAD engineer , you will build and support the ... flows, and resolve project-specific issues + Work closely with worldwide CPU physical design teams, and provide methodology guidance, tools/flows support and… more
- Qualcomm (Santa Clara, CA)
- …to define, develop and drive CPU timing closure for Oryon CPU Cores. As a CPU Physical Design Timing Engineer , you will work with microarchitecture and RTL ... and also useful in enabling CPU timing infrastructure and methodology impacting multiple CPU projects in Qualcomm. You will...out the root cause of timing miscorrelation at different design levels in functional and test mode, propose solutions.… more
- Meta (Sunnyvale, CA)
- …System on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Engineer , Physical Design Responsibilities: 1. Develop and own ... **Summary:** Meta is hiring ASIC Physical Design Engineers within our Infrastructure...data-path intensive designs 24. Experience in the 3D-IC technology, methodology , and advanced packaging 25. Experience in validating Power… more
- Qualcomm (Santa Clara, CA)
- …good exposure to high frequency design convergence for physical design with PPA targets and PDN methodology . + Masters/Bachelors Degree in ... smarter, connected future for all. As a Qualcomm CPU Engineer , you will lead innovative Central Processing Unit (CPU)...Business Units. Minimum Skill/Experience: + 2-10 yrs experience in Physical Design and timing signoff for high… more
- NVIDIA (Santa Clara, CA)
- …to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Physical Design Engineer to join our dynamic and growing team. If ... intelligence. What you'll be doing: + Drive next generation physical design work to achieve best in...of circuits and SPICE, as well as experience in methodology and/or flow development and automation. NVIDIA is widely… more
- Google (Sunnyvale, CA)
- …Experience leading one or more aspects of physical design or physical design flow/ methodology , to successful tape-outs and shipping silicon. + ... analysis and timing ECO creation, timing margins). + Experience with Electronic Design Automation (EDA) tools (ie, Primetime, Tempus, Timevision, STAR-RC) and EDA… more
- Qualcomm (Santa Clara, CA)
- …for physical design related issues is a must. Deep understanding of physical design flow and methodology is preferred. Minimum Requirements: - 2+ ... will be working on low power next generation Wifi subsystem related Physical design implementation. You will also be actively involved in Floor Planning (FP),… more
- Google (Sunnyvale, CA)
- …Experience leading one or more aspects of physical design or physical design flow/ methodology , to successful tape-outs and shipping silicon. + ... Experience in extraction of design parameters, QoR metrics, and analyzing data trends. +...systems. In this role, you will work on the physical implementation of ASICs using advanced technology nodes. You… more
- Google (Mountain View, CA)
- …STA and sign-off. Preferred qualifications: + Experience with ASIC design flows and methodology of Physical design . + Experience in low power design ... or a related field, or equivalent practical experience. + 4 years of experience in Physical Design . + Experience in one or more synthesis/PnR tools (eg, Genus,… more
- NVIDIA (Santa Clara, CA)
- …timing paths through ECOs including crosstalk and noise analysis. + Expertise in physical design and optimization eg, placement, routing, cell sizing, buffering, ... We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If...experience to improve timing convergence flows working with the methodology teams. What we need to see: + BS… more
- Broadcom (San Jose, CA)
- … methodology , power planning and analysis, timing closure, signal integrity and physical design checks. Participate in large complex design ... you apply.** **Job Description:** Broadcom is lookign for ASIC implementation engineer with demonstrated expertise in multiple disciplines including synthesis, … more