- SanDisk (Milpitas, CA)
- …**Digital Physical Design Engineer ** to work whole digital SPR flow from RTL to GDS, include Synthesis , DFT scan insertion, PNR, STA timing analysis, ... ICC2, Innovus, PT, StarRC ESSENTIAL DUTIES AND RESPONSIBILITIES: + ** Synthesis and DFT scan insertion** + Familiar timing constraint...A minimum of 3 years in Physical design digital RTL to GDS flow. + **Education** : Bachelor's or… more
- SanDisk (Milpitas, CA)
- …all aspects of digital design in NAND Flash memory, focusing on micro architecture, RTL design, verification, logic synthesis , and timing analysis to deliver a ... of innovation. We are looking for an experienced Principal Engineer to lead and deliver projects for our Memory...Logic design flow from RTL to GDSII ( RTL coding, simulation, synthesis , static timing analysis,… more
- SanDisk (Milpitas, CA)
- …all aspects of digital design in NAND Flash memory, focusing on micro architecture, RTL design, verification, logic synthesis , and timing analysis to deliver a ... of innovation. We are looking for an experienced Staff Engineer to lead and deliver projects for our Memory...Logic design flow from RTL to GDSII ( RTL coding, simulation, synthesis , static timing analysis,… more
- SanDisk (Milpitas, CA)
- …DUTIES AND RESPONSIBILITIES:** + Drive all aspects of physical design, including logic synthesis , place and route (P&R), and timing analysis for NAND Flash memory ... and area (PPA) targets + Collaborate closely with front-end RTL teams and back-end implementation engineers on physical verification,...date of **Dec 2024 - May/June 2025** + Knowledge synthesis , place & route, STA timing analysis and physical… more
- Broadcom (San Jose, CA)
- …Sign-In before you apply.** **Job Description:** **Broadcom is looking for a senior level RTL synthesis engineer . In this highly visible role, you will ... years of experience in Physical design.** + **Expert in Logic/Physical Synthesis using advanced optimization techniques and generating optimized Gate Level Netlist… more
- Broadcom (San Jose, CA)
- …apply.** **Job Description:** **Broadcom is looking for a high-speed DSP SerDes RTL designer. Qualifications include:** + **MS or PhD in Electrical Engineering or ... years of experience in high speed ADC based SerDes RTL design.** + **Proficient with Verilog-HDL/System Verilog coding for...and cost over the project lifetime.** + **Experience in synthesis , CDC, static timing analysis.** + **Exposure to SDF… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …but is not limited to: + Digital microarchitecture definition and documentation + RTL logic design, debug and functional verification + Strong background in DSP and ... of Lint checks and proper resolution of errors + Understanding synthesis timing constraints, static timing analysis and constraint development + Understanding… more
- NVIDIA (Santa Clara, CA)
- …methodologies + Build flows for methodologies incorporating logic/physical synthesis , design planning, equivalence checking for industry-leading chip designs ... , Tcl, C/C++ + Knowledge or experience with logic synthesis , physical design, formal equivalence checking. + Proven track...Learning + Experience in other ASIC methodologies such as RTL Lint, CDC, DFT or STA. + Experience with… more
- NVIDIA (Santa Clara, CA)
- …performance requirements and system limitations. + Craft micro-architecture, implement in RTL , and deliver a fully verified, synthesis /timing clean design. ... We are now looking for a Senior ASIC Design Engineer . NVIDIA is seeking ASIC Design Engineers to implement...caches. + Great understanding of ASIC design flow including RTL design, verification, logic synthesis and timing… more
- NVIDIA (Santa Clara, CA)
- …collaboration skills. Ways to stand out from the crowd: + Prior experience in RTL design (Verilog), verification and synthesis . + Proficiency in C++, Perl, ... a dedicated and motivated Software developer with particular interest in algorithms and RTL Design. Understanding both Software and Hardware principles will be a key… more
- NVIDIA (Santa Clara, CA)
- …low power circuits (power gating, decaps, multi-vt, etc..) is a plus. + Experience with RTL , logic synthesis and verification is a plus. + Mixed signal circuit ... We are now looking for a Senior Circuit Design Engineer ! NVIDIA stands at the intersection of hardware excellence...design and physical implementation of custom digital IPs from RTL to layout using industry standard tools and custom… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …R&D teams to win opportunities* Run Verilog simulations to enable IP benchmarking* Run RTL synthesis for area and timing analysis* Present IP demos to customers* ... an impact on the world of technology. Senior Applications Engineer - DDR Design IPJob Location: San Jose, CAJob...presales of DDR IP by generating collateral through simulations, synthesis and publications. As you grow into more senior… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …on the world of technology. This opportunity is for an engagement focused Product Engineer (PE) in the Digital and Signoff Group (DSG) at Cadence. The Cadence DSG ... You will be a highly motivated, optimistic, and energetic engineer with a good appreciation of ASIC design methodologies...with a good appreciation of ASIC design methodologies from RTL to GDSII with a strong history of self-improvement… more
- NVIDIA (Santa Clara, CA)
- …and intelligence. We are now looking for a motivated Senior ASIC Physical Design Engineer , Netlisting to join our dynamic and growing team. If you want to challenge ... asynchronous checking including clock domain crossing checks and MTBF analysis, logic synthesis , netlist quality checks, etc. + Help in all aspects of physical… more
- NVIDIA (Santa Clara, CA)
- …In-silicon measurement, Reset and Boot controllers. + You will be responsible for the RTL design, logic synthesis , and timing analysis of several modules. + ... is looking for a Senior Reset and Boot ASIC Engineer to join our System ASIC team! NVIDIA has...Chip Boot + Solid frontend ASIC design skills, including RTL design, asynchronous and synchronous Reset design, synthesis… more
- NVIDIA (Santa Clara, CA)
- …required as is a deep understanding of ASIC design flow including RTL design, verification, logic synthesis , prototyping, DFT, timing analysis, floor-planning, ... We are now looking for a Logic Design Engineer with Physical Design background! As a member...working closely with the physical design team on implementation, synthesis and timing closure as well as working on… more
- NVIDIA (Santa Clara, CA)
- …advanced silicon processes. We're responsible for NVIDIA's front-end ASIC software including RTL synthesis , equivalence checking, and early physical design and ... and see how you can make a lasting impact on the world. Are you a computer engineer with a passion for automation of VLSI ASIC design? Be part of a diverse team… more
- Broadcom (San Jose, CA)
- …will involve in engineering implementation spec writing from marketing/system requirements, RTL design and verification, synthesis , static timing analysis. You ... of system design tradeoffs for high volume applications. Must have good RTL experience including specification, design, verification, and synthesis . Must have… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a motivated Senior ASIC Design Engineer to join our dynamic and growing team in our Circuit Solutions Group! NVIDIA has continuously ... the power and performance of NVIDIA's next generation GPUs + Partner with RTL and Design Verification engineers to ensure delivery meets performance and quality… more
- NVIDIA (Santa Clara, CA)
- …interpersonal skills and ability to collaborate with multiple teams. + Experience in RTL design (Verilog), verification and logic synthesis . + Strong coding ... The clocks group is looking for a top-notch ASIC engineer to join the team. The Team is responsible...closure to innovate and implement new Clocking topologies in RTL . + Collaborate with Physical design and timing team… more
