• SanDisk (Milpitas, CA)
    …forward. **Job Description** We are looking for an experienced **Digital Physical Design Engineer ** to work whole digital SPR flow from RTL to GDS, include ... Synthesis, DFT scan insertion, PNR, STA timing analysis, IRdrop power analysis, DRC/LVS verification. Experienced...and analysis timing, routing issue in routeOpt stage, + ** STA timing analysis** + MMMC timing analysis using PT… more
    DirectEmployers Association (10/10/25)
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  • SanDisk (Milpitas, CA)
    …and back-end implementation engineers on physical verification, static timing analysis ( STA ), and tape-out readiness + Apply deep knowledge of design principles ... date of **Dec 2024 - May/June 2025** + Knowledge synthesis, place & route, STA timing analysis and physical verification with EDA CAD tools **Preferred Skills:** +… more
    DirectEmployers Association (09/11/25)
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  • STA Engineer

    Broadcom (San Jose, CA)
    …Sign-In before you apply.** **Job Description:** Broadcom is looking for a senior level STA engineer . In this highly visible role, you will be contributing to ... timing constraints for intricate SoC designs. + Perform static timing analysis ( STA ) using industry-standard tools (eg, PrimeTime, Tempus). + Define and implement… more
    Broadcom (10/09/25)
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  • STA Principal Application Engineer

    Cadence Design Systems, Inc. (San Jose, CA)
    …on SDC constraints, advanced OCV/SOCV concepts, derates, PBA timing, Distributed and Concurrent STA flows. . Work efficiently with R&D and customer to enable various ... timing analysis & ECO flows including newer advanced technologies. . Performing timing correlation, tool feature benchmarking, constraints validation, spice analysis on various tech nodes and customer designs. . Work on In-design timing ECO optimizations… more
    Cadence Design Systems, Inc. (08/14/25)
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  • Senior Timing Methodology Engineer

    NVIDIA (Santa Clara, CA)
    …inventiveness and intelligence. We are seeking an innovative Senior Timing Methodology Engineer to help drive sign-off strategies for the world's leading GPUs and ... and validate flows for Prime-Time , Prime-Shield and Tempus STA QoR metrics for sign-off flow, and tool for...std cells and custom IPs. + Develop flows/recommendations on STA sign-off to model deep submicron physical effects aging,… more
    NVIDIA (07/19/25)
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  • Senior ASIC Test Timing Engineer

    NVIDIA (Santa Clara, CA)
    …and intelligence. We are now looking for a motivated Senior ASIC Test Timing Engineer to join our dynamic and growing team. If you want to challenge yourself ... or MS (or equivalent experience) with 2+ years' experience in Timing and STA + Hands-on experience in full-chip/sub-chip Static Timing Analysis ( STA ) and… more
    NVIDIA (10/07/25)
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  • DFT Engineer

    Broadcom (San Jose, CA)
    …Account, please Sign-In before you apply.** **Job Description:** **Principal DFT Engineer ** Broadcom's ASIC Product Division is seeking candidates for a DFT ... metrics. It involves working with the Physical Design & STA team for DFT mode timing closure. The role...and other I/P DFT integration + Working closely with STA and DI Engineers design closure for test +… more
    Broadcom (09/05/25)
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  • Senior Async and IO Timing Methodology…

    NVIDIA (Santa Clara, CA)
    …inventiveness and intelligence. We are seeking a highly skilled Timing Methodology Engineer with expertise in asynchronous timing and I/O interface modeling to ... timing constraints, validating IO timing integrity, and enabling scalable STA methodologies across design hierarchies and technology nodes. We're looking… more
    NVIDIA (08/21/25)
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  • Senior ASIC Timing Engineer

    NVIDIA (Santa Clara, CA)
    …methodology on next generation CMOS technology. We are looking for a Senior ASIC Timing Engineer to join our dynamic and growing team! If you are problem solver and ... in Physical design/Timing. + Experience in full-chip/sub-chip Static Timing Analysis ( STA ), timing constraints generation and management, and timing convergence. +… more
    NVIDIA (09/09/25)
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  • Senior ASIC Physical Design and Timing…

    NVIDIA (Santa Clara, CA)
    …human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you want to challenge yourself ... and Timing + Hands-on experience in full-chip/sub-chip Static Timing Analysis ( STA ), timing constraints generation and management, and timing convergence. +… more
    NVIDIA (08/23/25)
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  • Senior Methodology Engineer , CAD Tool…

    NVIDIA (Santa Clara, CA)
    …a lasting impact on the world! We are currently looking for a Senior Methodology Engineer to develop and support our CAD tooling in our Circuit Solutions Group ! In ... VLSI CAD flows and methodology + Timing closure and STA tool experience required + Good programming skills in...+ Experience with .lib characterization flow or other related STA flows + Enjoy working with multiple levels and… more
    NVIDIA (07/22/25)
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  • Senior Circuit Design Engineer

    NVIDIA (Santa Clara, CA)
    We are now looking for a Senior Circuit Design Engineer ! NVIDIA stands at the intersection of hardware excellence and AI breakthrough, where every line of code and ... execution, including Custom/Semi-Custom Circuit Design, Synthesis, Auto Place and Route, STA , and PVerf. + Proven capability in Post-Silicon characterization and… more
    NVIDIA (10/10/25)
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  • Senior ASIC Physical Design Engineer

    NVIDIA (Santa Clara, CA)
    …and intelligence. We are now looking for a motivated Senior ASIC Physical Design Engineer , Netlisting to join our dynamic and growing team. If you want to challenge ... flow development. + Strong experience in full-chip/sub-chip Static Timing Analysis ( STA ), timing constraints generation and management, and timing convergence. +… more
    NVIDIA (10/07/25)
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  • Senior Custom Timing Engineer - Circuits

    NVIDIA (Santa Clara, CA)
    We are now looking for a motivated Senior Custom Timing Engineer to join our dynamic and growing Circuit Solutions Group! If you are looking for a challenging and ... we need to see: + Expertise and in depth knowledge of industry standard STA tools such as NanoTime and PrimeTime. + Experience in timing constraints generation &… more
    NVIDIA (09/20/25)
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  • CAD Flow Development Engineer

    NVIDIA (Santa Clara, CA)
    …and see how you can make a lasting impact on the world. Are you a computer engineer with a passion for automation of VLSI ASIC design? Be part of a diverse team ... + Experience in other ASIC methodologies such as RTL Lint, CDC, DFT or STA . + Familiarity with Machine Learning/Deep Learning NVIDIA is widely considered to be the… more
    NVIDIA (09/05/25)
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  • Senior ASIC Design Engineer - Circuits

    NVIDIA (Santa Clara, CA)
    We are now looking for a motivated Senior ASIC Design Engineer to join our dynamic and growing team in our Circuit Solutions Group! NVIDIA has continuously ... + Work with front-end teams to overlook correctness of the design (Lint/NA/CDC/Synthesis/DFT/LEC/ STA ) + Partner and work with back-end team until chip tape-out. +… more
    NVIDIA (08/27/25)
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  • Physical Design Methodology Engineer

    NVIDIA (Santa Clara, CA)
    …in advanced Clock tree synthesis methods and techniques + Strong background in STA , extraction, timing and RC correlation + Background with design rules in advanced ... nodes and their impact on DRC closure and PPA optimization + Understanding of power intent files such as UPF, and use of FSDB/SAIFs for power optimization + Understanding of hierarchical design, pinning and budgeting flows + Experience with power distribution… more
    NVIDIA (09/23/25)
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  • Senior High-Performance ASIC Timing…

    NVIDIA (Santa Clara, CA)
    …3+ years' experience in ASIC Design and Timing + Hands-on experience in STA tools, ECO implementation, and timing closure of high-speed designs. + Strong background ... and experience in timing constraints generation, clocking, process variations and signal integrity + Proficiency in programming and scripting languages, such as, Perl, Tcl, Python, etc. and ability to understand and improve existing flows and methodologies. +… more
    NVIDIA (09/23/25)
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  • Senior Synthesis Flow CAD Engineer

    NVIDIA (Santa Clara, CA)
    …in other ASIC methodologies such as RTL Lint, CDC, DFT or STA . + Experience with compute farm interaction: software deployment, performance optimization, containers, ... etc. NVIDIA is widely considered to be the leader of AI computing, and one of the technology world's most desirable employers. We have some of the most forward-thinking and talented people in the world working for us. If you're creative and autonomous, we want… more
    NVIDIA (09/09/25)
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  • Lead Speed and Reliability Engineer - DFP

    NVIDIA (Santa Clara, CA)
    …plus, related to timing, speed, reliability and power. + Familiarity with STA timing closure, circuit design, noise characterization, product binning methods and/or ... performance/power optimization techniques. Ways to stand out from the crowd: + Familiarity with statistical methods and tools for data analysis + Background with substrate and power supply noise analysis and mitigation + A "go-getter, can get it done" attitude… more
    NVIDIA (08/28/25)
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