• Senior ASIC Test

    NVIDIA (Santa Clara, CA)
    …life's work, to amplify human inventiveness and intelligence. We are now looking for a motivated Senior ASIC Test Timing Engineer to join our dynamic and ... inventiveness and intelligence. What you'll be doing: + Drive timing analysis and closure of Nvidia's GPUs, CPUs, DPUs...DFX, Clocks, and other teams in coming up with timing closure strategy, creating timing constraints, driving… more
    NVIDIA (10/07/25)
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  • Senior ASIC Timing Engineer

    NVIDIA (Santa Clara, CA)
    …design tradeoffs and methodology on next generation CMOS technology. We are looking for a Senior ASIC Timing Engineer to join our dynamic and growing team! ... balance between frequency and power/area/congestions/yield/etc. + Work on all aspects of DFT/ Test timing such as timing constraints, timing analysis, … more
    NVIDIA (09/09/25)
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  • Senior Silicon Pre-to-Post Validation Lead,…

    Google (Fremont, CA)
    Senior Silicon Pre-to-Post Validation Lead, Raxium _corporate_fare_ Google _place_ Fremont, CA, USA **Advanced** Experience owning outcomes and decision making, ... + 15 years of experience in Application-Specific Integrated Circuit/System on Chip ( ASIC /SoC) design, with a focus on both digital logic design and Design… more
    Google (10/04/25)
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