- Google (Sunnyvale, CA)
- …measuring chip power consumption. + Develop design improvements to increase power efficiency . + Collaborate with cross-functional teams in defining power ... using EDA tools such as PTPX, PowerArtist, or PrimePower. + Experience driving power - efficiency improvement in chip designs. + Experience with pre-silicon vs… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior ASIC Power Engineer ! NVIDIA is seeking extraordinary power engineers to design hardware accelerators and processors on ... to extend the state of the art performance and efficiency + You are expected to understand the design...are expected to understand the design and implementation, develop power metrics and drive power reductions +… more
- NVIDIA (Santa Clara, CA)
- We are now looking for an ASIC Design Efficiency Engineer . NVIDIA is seeking extraordinary methodology engineers to design hardware accelerators and ... and system designs to extend the state of the art performance and efficiency . + Understand the design and implementation, develop methodology and infrastructure to… more
- Google (Sunnyvale, CA)
- …will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency , and integration. As a Design Engineer , you will play ... + Experience with industry-standard EDA tools for simulation, synthesis, and power analysis. Preferred qualifications: + Master's degree or PhD in Electrical… more
- Google (Sunnyvale, CA)
- …with System Level Test (SLT) or product engineering. + Experience with ASIC or SoC prototype bring-up, debug, functional verification or functional manufacturing ... team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to...use Google services around the world. We prioritize security, efficiency , and reliability across everything we do - from… more
- NVIDIA (Santa Clara, CA)
- …power data, and driving ASIC teams to improve their units' power efficiency ; and is responsible for researching, developing, and deploying methodologies ... We are now looking for a Senior Power Architecture and Optimization Engineer ! NVIDIA... power analysis tools, to help improve product power efficiency . + Develop and share best… more
- NVIDIA (Santa Clara, CA)
- …power data and driving ASIC teams to improve their units' power efficiency ; and is responsible for researching, developing, and deploying methodologies to ... We are looking for a Senior Emulation Power Engineer ! NVIDIA prides in having...concepts of energy consumption, estimation, data movement and low power design. + Familiarity with Verilog and ASIC… more
- Meta (Sunnyvale, CA)
- **Summary:** Meta is looking for an experienced ASIC Packaging Engineer , Signal Integrity, and Power Integrity focus for its ASIC packaging team to ... to develop packaging solutions that are optimal for our ASIC roadmap. We are building a competency in Packaging...such as 2.5D/3D and heterogeneous integration to improve bandwidth, power efficiency and package form factor for… more
- Qualcomm (Santa Clara, CA)
- …are highly optimized for the needs of the server product. **Position: Server Chipset Power Engineer ** We are seeking a highly experienced Server Chipset Power ... innovative solutions that push the limits of performance, energy efficiency , and scalability. Our focus is on developing server-class... and silicon/system limits + Strong fundamentals in digital ASIC design and power of CMOS circuits… more
- NVIDIA (Santa Clara, CA)
- …a trailblazer at the forefront of graphics and artificial intelligence performance, efficiency , and innovation. From our roots as a groundbreaking graphics company, ... industries. NVIDIA Silicon Solutions Group is seeking a versatile engineer to be part of the HW ArchDev team....Build roadmaps of system level features to address low power , low noise, perf/watt efficient product needs by doing… more
- Cisco (San Jose, CA)
- …for universal adaptability, delivering high speed without sacrificing programmability, buffering, power efficiency , scale, or feature flexibility. The Cisco ... Principal Engineer - Silicon One Software Apply (https://jobs.cisco.com/jobs/Login?projectId=1443934) +...Team** Cisco Silicon One is the center of Cisco's ASIC design and is driving the development of next-generation… more
- Palo Alto Networks (Santa Clara, CA)
- …integrity analysis of ASIC and multi-chip-module designs + Model and analyze power delivery networks for ASIC /package/module and PCB + Create SI test plan ... Experience** + Strong background in hands-on design and validation of high-speed PCB and ASIC package development + Power integrity design and analysis and well… more
- Cisco (San Jose, CA)
- …from the DSP and ASIC teams is key to optimizing performance and power efficiency . You'll contribute to system design, develop architectures, and support ... Principal DSP Engineer - Coherent Optical Transmission Systems - Acacia Apply...ASIC design and verification. Work closely with colleagues across various… more
- Cisco (San Jose, CA)
- …for universal adaptability, delivering high speed without sacrificing programmability, buffering, power efficiency , scale, or feature flexibility. The Cisco ... Software Engineer - Networking Apply (https://jobs.cisco.com/jobs/Login?projectId=1441274) + Location:San Jose,...are** **Cisco Silicon One is the center of Cisco's ASIC design and is driving the development of next-generation… more
- Google (Sunnyvale, CA)
- …will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency , and integration. As a SoC Design Engineer , you will ... Experience with industry-standard EDA tools for simulation, synthesis and power analysis. Preferred qualifications: + Master's degree or PhD...on computer architecture. + 10 years of experience in ASIC design with 3 years of experience working on… more
- Cisco (San Jose, CA)
- …for universal adaptability, delivering high speed without sacrificing programmability, buffering, power efficiency , scale, or feature flexibility. The Cisco ... Senior Software Engineer Apply (https://jobs.cisco.com/jobs/Login?projectId=1443844) + Location:San Jose, California, US...Team** Cisco Silicon One is the center of Cisco's ASIC design and is driving the development of next-generation… more
- Cisco (San Jose, CA)
- …for universal adaptability, delivering high speed without sacrificing programmability, buffering, power efficiency , scale, or feature flexibility. The Cisco ... Senior Technical Leader Software Engineer , Cisco Silicon One (L2/L3) Apply (https://jobs.cisco.com/jobs/Login?projectId=1441663) +...Team** Cisco Silicon One is the center of Cisco's ASIC design and is driving the development of next-generation… more
- Meta (Menlo Park, CA)
- **Summary:** Meta is seeking a Hardware Systems Engineer to join our Release to Production (RTP) team working on new NPI hardware. Our servers and data centers are ... software and hardware technologies for AI at datacenter scale.Hardware Systems Engineer in RTP work closely with HW/SW co-design teams, hardware designers,… more
- NVIDIA (Santa Clara, CA)
- NVIDIA's GPUs and SOCs are the world leaders in power , performance and efficiency . We are continually innovating to deliver new and creative, unusual solutions ... we are now seeking a hard-working Senior Package Layout Engineer who is committed to making a difference in...Layout team, you will collaborate to implement high speed/density ASIC packages. + Perform substrate breakout patterns for … more
- Google (Mountain View, CA)
- …+ Experience with logic synthesis techniques to optimize RTL code, performance and power , as well as low- power design techniques. + Experience with a ... Engineering, Computer Engineering or Computer Science. + Experience with ASIC design methodologies for clock domain checks, reset checks...methodologies for clock domain checks, reset checks and low power design. + Knowledge in one of these areas:… more