- Qualcomm (Santa Clara, CA)
- …SoC Implementation Team is looking for skilled engineers to focus on timing constraints development, power analysis, STA , and timing closure for ... This is an excellent opportunity to join the Snapdragon implementation team, which is responsible for SoCs in sub-3nm...and low-power multi-voltage domain crossings, and signoff with static timing analysis. + Collaborate closely with RTL design… more
- Meta (Sunnyvale, CA)
- …on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Implementation Engineer - Timing Responsibilities: 1. Develop Timing Constraints ... scripts and Methodology for all FE-tools including ( Synthesis, STA ). 7. Work closely with the Design ...them with the handoff tasks. 8. Interact with Physical Design Engineers and provide them with timing /congestion… more
- NVIDIA (Santa Clara, CA)
- …or MS (or equivalent experience) with 3+ years' experience in ASIC Design and Timing + Hands-on experience in STA tools, ECO implementation , and ... timing including setting up timing constraints, timing analysis and closure, ECO implementation , and...to collaborate with cross-functional teams. + Strong understanding of timing and physical design fundamentals Ways to… more
- Meta (Sunnyvale, CA)
- …RTL DFT Analysis and improve the DFT coverage for Stuck-at faults. 7. Develop Timing Constraints for RTL-Synthesis and PrimeTime- STA for the blocks and the ... Methodology for all FE-tools including (Lint, CDC, RDC, Synthesis, STA , Power). 10. Work closely with the Design...them with the handoff tasks. 11. Interact with Physical Design Engineers and provide them with timing /congestion… more
- Meta (Sunnyvale, CA)
- …RTL DFT Analysis and improve the DFT coverage for Stuck-at faults. 7. Develop Timing Constraints for RTL-Synthesis and PrimeTime- STA for the blocks and the ... Methodology for all FE-tools including (Lint, CDC, RDC, Synthesis, STA , Power). 9. Work closely with the Design...supporting them with the handoff tasks. Interact with Physical Design Engineers and provide them with timing /congestion… more
- Cisco (San Jose, CA)
- …STA tools and scripting for automation, you excel at identifying and resolving timing issues across all design levels. You will collaborate with Front-end and ... to understand chip architecture and guide them in refining design and timing constraints for seamless physical...or related experience. * Experience with microarchitecture and RTL implementation . * Experience with digital design concepts… more
- Amazon (Sunnyvale, CA)
- …to understand the design and create timing constraints. * Check the RTL design for clean synthesis run, perform STA and LEC on netlist. * Work with RFIC ... equivalent experience. * 7+ years of experience in ASIC implementation , ie, synthesis, STA and working with...Communications Engineering. * 10+ years of experience in ASIC implementation . * Experience in leading physical design .… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …good understanding of noise, cross-talk, and OCV effects, among others. + Experience with large design STA and Timing Closure. + Familiar with ECO techniques ... interact with both Front End ( Design / DFT) and Back End Implementation Teams (P&R). + Proficient in STA and methodologies for timing closure, and have a… more
- Meta (Sunnyvale, CA)
- …to develop reset groups and corresponding reset sequence for RDC. 10. Develop timing constraints for RTL-synthesis and PrimeTime- STA for blocks and top-level ... online on this web page. **Required Skills:** ASIC Engineer, Implementation Responsibilities: 1. Run logic/physical synthesis using advanced optimization techniques… more
- SpaceX (Sunnyvale, CA)
- …will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design , validation, product engineering, ASIC implementation ). In this ... voltage drop, logic equivalency and other signoff checks) + Develop/improve physical design methodologies and automation scripts for various implementation steps… more
- Google (Sunnyvale, CA)
- … design flows, and methodologies including synthesis, place and route, Static Timing Analysis ( STA ), formal verification, Change Data Capture (CDC), and power ... at Google (https://careers.google.com/benefits/) . + Perform full chip clock planning. Create timing constraints and own the physical implementation of clock… more
- NVIDIA (Santa Clara, CA)
- …inventiveness and intelligence. What you will be doing: + Developing innovative physical design methodologies for implementation of GPU, CPU and SOCs, with ... tree synthesis methods and techniques + Strong background in STA , extraction, timing and RC correlation +...timing and RC correlation + Good understanding of design rules in advanced nodes and their impact on… more
- Broadcom (San Jose, CA)
- …with VLSI design tools for Place&Route, Verilog simulation, DRC/LVS verification, Timing analysis ( STA ), Scripting languages - Tcl?Perl/ Python + Proficiency ... ASICs. Key competencies required are: + Working experience in (digital) physical design implementation of large scale ASICs (Multi-100 million gates complexity).… more
- Google (Sunnyvale, CA)
- …related field, or equivalent practical experience. + 7 years of physical design experience with industry-standard tools, languages, and methodologies relevant to the ... of silicon-based ICs and chips. + Experience in logic synthesis, PnR, timing closure, and static timing analysis. Preferred qualifications: + Master's… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …our communities, and each other-every day. Key Responsibilities The Senior Principal Design Engineer will define the DFT Architecture for the next generation SoCs. ... This person will also be responsible for the implementation & verification including Scan, PMBIST, JTAG and other...constraints as well as perform RTL and gate level (no- timing and timing ) simulations to verify DFT… more