- NVIDIA (Santa Clara, CA)
- …make a lasting impact on the world! We are now looking for an Low Power Design/Verification ASIC Engineer - New College Grad 2025. We continue to rapidly ... to deliver exceptional perf/watt solutions in a wide range of sectors. Come join NVIDIAs Low Power DV team to develop state of the art GPUs to power AI,… more
- Meta (Sunnyvale, CA)
- …for individuals with experience in backend implementation from Netlist to GDSII in low power and high-performance designs to build efficient System on Chip ... (SoC) and IP for data center applications. **Required Skills:** ASIC Engineer , Physical Design Responsibilities: 1. Develop...and power grid planning. 19. Experience with low power implementation, power gating,… more
- Meta (Sunnyvale, CA)
- …Post-Silicon teams towards creating a first-pass silicon success. **Required Skills:** ASIC Engineer , Formal Verification Responsibilities: 1. Provide technical ... **Summary:** Meta is hiring ASIC Formal Verification Engineer within the...in clock domain crossing, IP-XACT based register verification and low power 21. Experience with development of… more
- Meta (Sunnyvale, CA)
- …Memories. 22. Knowledge of STA signoff and understanding of AOCV, POCV 23. Experience with low power techniques for reducing power . 24. Experience with EDA ... on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Implementation Engineer - Synthesis Responsibilities: 1. Run Logic/Physical… more
- Meta (Sunnyvale, CA)
- …Memories. 20. Knowledge of STA signoff and understanding of AOCV, POCV 21. Experience with low power techniques for reducing power . 22. Experience with EDA ... on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Implementation Engineer - Synthesis Responsibilities: 1. Run Logic/Physical… more
- NVIDIA (Santa Clara, CA)
- …Systems design. + Experience with multiple clock domains and asynchronous interfaces. + Experience in low power design and low power architecture. + ... NVIDIA is looking for an ASIC Design Engineer to join our Memory Subsystem Team! As an ASIC Design engineer at NVIDIA, you'll join a group of… more
- Amazon (Sunnyvale, CA)
- …implementation. * Experience in leading physical design. * Strong exposure to UPF flow for low power design. * Strong written and verbal skills * Experience of ... Kuiper is an initiative to launch a constellation of Low Earth Orbit satellites that will provide low...flow for various technology nodes. * Work with the ASIC design and DFT teams to understand the design… more
- Amazon (Cupertino, CA)
- …design quality and making the right trade-offs. Key job responsibilities As an ASIC Design Engineer , you will: * Develop and implement high-performance, area ... Description Amazon Web Services provides a highly reliable, scalable, low -cost infrastructure platform in the cloud that powers hundreds of thousands of businesses… more
- Broadcom (San Jose, CA)
- …Tcl scripting skill Other highly desirable experience: o 802.3 Ethernet or NIC experience. o Low power design skills o Layer 1 through Layer 4 experience The ... challenged and gain valuable experience towards enhancing a successful career in ASIC design. You will involve in engineering implementation spec writing from… more
- Google (Mountain View, CA)
- …(IP) design for clocking, interconnects or peripherals. + Experience with methodologies for low power estimation, timing closure, or synthesis. + Experience with ... logic synthesis techniques to improve RTL code, performance and power as well as low - power ...design techniques. + Experience with ARM-based SoCs, interconnects and ASIC methodology. + Experience with a scripting language like… more
- Google (Mountain View, CA)
- …years of industry experience with IP design. + Experience with methodologies for low power estimation, timing closure, synthesis. + Experience with methodologies ... like Python or Perl. + Experience with ARM-based SoCs, interconnects and ASIC methodology. Preferred qualifications: + Master's degree or PhD in Electrical… more
- Amazon (Sunnyvale, CA)
- …to post-silicon validation. The team works backwards from customer requirements to build super- low power , energy efficient designs that include the latest in AI, ... video processing, low power communications and CMOS fabrication technology. Key job responsibilities - Evaluate 3rd party IP blocks - Estimate power ,… more
- Amazon (Sunnyvale, CA)
- …to post-silicon validation. The team works backwards from customer requirements to build super- low power , energy efficient designs that include the latest in AI, ... video processing, low power communications and CMOS fabrication technology. Key job responsibilities - Use and/or build bit accurate C models - Evaluate block… more
- Amazon (Cupertino, CA)
- …which is a machine learning inference accelerator designed to deliver high performance at low cost. If this sounds exciting to you - come build the future with ... in various aspects of physical design: full chip floorplanning, circuit analysis, power /clock distribution, timing optimization, place and route, power integrity… more
- Qualcomm (Santa Clara, CA)
- …IP based full chip debug is preferred. + 7+ yrs. of working experience in ASIC Design + Low power micro-architecture, Design, Power ... to volume chip production for at least one product cycle is preferred **Keywords** : ASIC ; SOC; Low Power ; Power estimates; Power Intent; Power … more
- Qualcomm (Santa Clara, CA)
- …transformation to help create a smarter, connected future for all. As a Qualcomm ASIC Engineer , you will define, model, design (digital and/or analog), optimize, ... IP (block/SoC) development for a variety of high performance, high quality, low power world class products. Qualcomm Engineers collaborate with cross-functional… more
- NVIDIA (Santa Clara, CA)
- …of concepts of energy consumption, estimation, data movement and low power design. + Familiarity with Verilog and ASIC design principles, including ... We are now looking for a Senior Power Architecture and Optimization Engineer ! NVIDIA...Our team is responsible for analyzing fullchip and unit-level power data, and driving ASIC teams to… more
- NVIDIA (Santa Clara, CA)
- …of concepts of energy consumption, estimation, data movement and low power design. + Familiarity with Verilog and ASIC design principles, including ... We are looking for a Senior Emulation Power Engineer ! NVIDIA prides in having...Our team is responsible for analyzing fullchip and unit-level power data and driving ASIC teams to… more
- NVIDIA (Santa Clara, CA)
- …of concepts of energy consumption, estimation, data movement and low power design. + Familiarity with Verilog and ASIC design principles, including ... We are now looking for a Power Architecture and Optimization Engineer -...You will collaborate with Architects, Performance Engineers, Software Engineers, ASIC Design Engineers, and Physical Design teams to study… more
- NVIDIA (Santa Clara, CA)
- …alignment. What you'll be doing: + Build roadmaps of system level features to address low power , low noise, perf/watt efficient product needs by doing ... industries. NVIDIA Silicon Solutions Group is seeking a versatile engineer to be part of the HW ArchDev team..../performance optimization. + Strong EE fundamentals on digital design, low power design, DVFS, control systems, signal… more