- SpaceX (Sunnyvale, CA)
- Sr. SOC / ASIC Physical Design Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where humanity is out ... this possible, with the ultimate goal of enabling human life on Mars. SR. SOC / ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're… more
- NVIDIA (Santa Clara, CA)
- …Design Engineers to design and implement the world's leading GPU and SoC 's. With the System- ASIC team, you will contribute to designing multiple products ... NVIDIA is looking for a Senior ASIC Design Engineer to join our...of several modules. + Integrate modules into the overall SOC design and work closely with other… more
- Meta (Sunnyvale, CA)
- **Summary:** Meta is hiring ASIC Physical Design Engineers...design of an end-to-end IP or integration of ASIC / SoC design and point out ... ) and IP for data center applications. **Required Skills:** ASIC Engineer, Physical Design Responsibilities:...design and timing closure 12. Experience with large SOC designs (>20M gates) with frequencies over 1GHZ 13.… more
- NVIDIA (Santa Clara, CA)
- …interconnect and floorplan improvement opportunities + Solve timing and routing congestion issues with physical and ASIC design teams by influencing early ... seeking a talented ASIC Floorplan Engineer to design and implement the world's leading SoC 's...What you will be doing: + Working with architects, design leads, physical design leads… more
- Google (Sunnyvale, CA)
- …. + Work separately and collaboratively to create and review ASIC / SoC subsystem design architecture and microarchitecture specifications. ... Engineer, you will play an important role in designing ASIC / SoC hardware for Artificial Intelligence (AI) and...to evaluate features and their impact. + Work with physical design teams to ensure design… more
- SanDisk (Milpitas, CA)
- … development + Contribute to the development of best practices and methodologies for ASIC design within the organization + Optimize designs for power efficiency, ... architectures using advanced RTL techniques + Develop and optimize SoC subsystems, including CPU complex, DDR, Host, Flash, Debug,...design optimization + Proficiency in EDA tools for ASIC design and verification + Knowledge of… more
- NVIDIA (Santa Clara, CA)
- NVIDIA is seeking an outstanding Senior ASIC Design Engineer to design and implement the world's leading SoC 's and GPU's. This position offers the ... synthesis/timing clean design while working with the physical design team to ensure a routable...Systems design . + A deep understanding of ASIC design flow including RTL design… more
- Meta (Sunnyvale, CA)
- …Emulation Engineers in supporting them with the handoff tasks. Interact with Physical Design Engineers and provide them with timing/congestion feedback. ... practical experience **Preferred Qualifications:** Preferred Qualifications: 16. Experience with SOC Design Integration and Front-End Implementation. 17.… more
- Meta (Sunnyvale, CA)
- …Emulation Engineers in supporting them with the handoff tasks. Interact with Physical Design Engineers and provide them with timing/congestion feedback. ... practical experience **Preferred Qualifications:** Preferred Qualifications: 17. Experience in SOC Design Integration and Front-End Implementation. 18. Knowledge… more
- Amazon (Cupertino, CA)
- …Develop and execute design automation mechanisms and flows. * Work with physical design teams to achieve performance and area requirements. Mentorship & ... requirements including software applications, use models, system architecture and SoC architecture/micro-architecture solutions. * Participate in logic design … more
- Meta (Sunnyvale, CA)
- …for Power, Performance, and Area 18. 2. Floor Planning and Placement 19. 3. Physical Design Execution for Clock Tree Synthesis and Routing optimization 20. 4 ... to Job" online on this web page. **Required Skills:** ASIC Engineer, Implementation Responsibilities: 1. Run logic/ physical ...domain crossing checks. 9. Understand reset-architecture and work with design & FW teams to develop reset groups and… more
- NVIDIA (Santa Clara, CA)
- …5+ years' experience or MS (or equivalent experience) with 3+ years' experience in ASIC Design and Timing + Hands-on experience in STA tools, ECO implementation, ... next generation of high-performance IPs for CPU, GPU and SOC designs. + Owning static timing analysis and convergence...with cross-functional teams. + Strong understanding of timing and physical design fundamentals Ways to stand out… more
- Google (Sunnyvale, CA)
- …Computer Science, with an emphasis on computer architecture. + 10 years of experience in ASIC design with 3 years of experience working on security design . ... experiences, delivering unparalleled performance, efficiency, and integration. As a SoC Design Engineer, you will join a...to verify and debug RTL designs. + Work with physical design teams to ensure design… more
- Google (Mountain View, CA)
- …convergence, including STA and sign-off. Preferred qualifications: + Experience with ASIC design flows and methodology of Physical design . + Experience ... equivalent practical experience. + 4 years of experience in Physical Design . + Experience in one or...Performance, Area and Power. + Develop all aspects of ASIC RTL2GDS implementation for designs. + Manage physical… more
- Amazon (Sunnyvale, CA)
- …as with the RTL/Arch. Teams Basic Qualifications - BS in EE/CS - 7+ years in ASIC Physical Design from RTL-to-GDSII in FINFET technologies such as 5nm/7nm, ... that is powering the latest generation of Echo devices is looking for a Sr. Physical Design Engineer to continue to innovate on behalf of our customers. We are a… more
- Qualcomm (Santa Clara, CA)
- …future for all. QCTs Digital ASIC Team is actively seeking candidates for several physical design engineering positions in our SOC and core design ... be part of a team responsible for the complete Physical Design Flow and deliveries of complex,...Science, Engineering, or related field and 6+ years of ASIC design , verification, validation, integration, or related… more
- Meta (Sunnyvale, CA)
- … integration and ASIC architecture 10. Skilled in micro-architecture, RTL coding, design verification and SoC Integration of complex IPs 11. Experience in ... demonstrate and integrate advanced IP and AI accelerators into SOC / ASIC solutions to enable in-system testing and...collaboration with Digital Verification (DV) 3. Support back end physical design (PD) through STA and SDCs… more
- Qualcomm (Santa Clara, CA)
- …domain crossings, and signoff with static timing analysis. + Collaborate closely with RTL design and physical design teams to identify timing requirements ... design constraints to achieve timing closure of complex SoC cores. + Review and integrate HM constraints into...Science, Engineering, or related field and 4+ years of ASIC design , verification, validation, integration, or related… more
- Meta (Sunnyvale, CA)
- …Experience in SoC bus and interconnect protocols 12. Knowledge of physical design and low-power implementation 13. Experience with high-speed I/O protocols ... Work cross-functionally with adjacent chip-level teams such as Verification, Physical Design , and Design -for-Test **Minimum...design uArchitecture and RTL coding 9. Experience in SoC integration and ASIC architecture 10. Experience… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …portfolio. This is a pre-sales role. It is perfect for someone who has System/ ASIC / SoC design experience and great interpersonal and communication skills and ... and working with customers to develop solutions for their System/ ASIC / SoC designs using the Cadence Serdes IP...state-of-the-art SoC design implementation: RTL design , synthesis and static timing analysis, physical … more