We interpreted Mountain View, CA as Mountain View, CA. Other options include: Mountain View (Contra Costa County), CA
- SpaceX (Sunnyvale, CA)
- Sr. SOC / ASIC Physical Design Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where humanity is out exploring ... this possible, with the ultimate goal of enabling human life on Mars. SR. SOC / ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our… more
- SpaceX (Sunnyvale, CA)
- ASIC / SOC DV Engineer (Silicon Engineering) Sunnyvale, CA...for digital ASIC verification at block and system level + Write and review test plans, ... make this possible, with the ultimate goal of enabling human life on Mars. ASIC / SOC DV ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience… more
- SpaceX (Sunnyvale, CA)
- ASIC / SOC DFT Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where humanity is out exploring the stars is ... make this possible, with the ultimate goal of enabling human life on Mars. ASIC / SOC DFT ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience… more
- SpaceX (Sunnyvale, CA)
- Sr. SOC / ASIC Physical Design Methodology/CAD Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where humanity ... possible, with the ultimate goal of enabling human life on Mars. SR. SOC / ASIC PHYSICAL DESIGN METHODOLOGY/CAD ENGINEER (SILICON ENGINEERING) At SpaceX we're… more
- SpaceX (Sunnyvale, CA)
- Sr. SOC / ASIC DFT Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where humanity is out exploring the stars ... ultimate goal of enabling human life on Mars. SR. SOC / ASIC DFT ENGINEER (SILICON ENGINEERING) At SpaceX...(IST), boundary scan (IEEE 1149.1), functional testing in embedded systems , or board- level diagnostics, preferably using Siemens… more
- NVIDIA (Santa Clara, CA)
- …architects, ASIC designers, and verification engineers to design sophisticated system - level modules such as Floorsweep, In-silicon measurement, Reset and ... and Boot ASIC Engineer to join our System ASIC team! NVIDIA has continuously reinvented...SoC design/integration experience, including architecture and implementation of system - level functions like Reset or Chip Boot… more
- SanDisk (Milpitas, CA)
- …technological innovation. ESSENTIAL DUTIES AND RESPONSIBILITIES: + Lead the comprehensive SoC development process for ASIC controllers utilized in SanDisk ... precise ASIC project requirements and specifications. + Coordinate effectively with SoC Design, SoC Design Verification, ASIC Validation, DFT, Physical… more
- Meta (Sunnyvale, CA)
- …implement IP/ SoC verification plans, build verification test benches to enable IP/sub- system / SoC level verification 2. Develop functional tests based on ... **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization....and/or C/C++ based verification 10. 8+ years experience in IP/sub- system and/or SoC level verification… more
- Meta (Sunnyvale, CA)
- …implement IP/ SoC verification plans, build verification test benches to enable IP/sub- system / SoC level verification 2. Develop functional tests based on ... **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization....C/C++ based verification 9. 6+ years of experience in IP/sub- system and/or SoC level verification… more
- Meta (Sunnyvale, CA)
- …implement IP/ SoC verification plans, build verification test benches to enable IP/sub- system / SoC level verification 2. Develop functional tests based on ... **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization....and/or C/C++ based verification 10. 8+ years experience in IP/sub- system and/or SoC level verification… more
- Meta (Sunnyvale, CA)
- …implement IP/ SoC verification plans, build verification test benches to enable IP/sub- system / Soc level verification, and develop functional tests based ... to build IP and System On Chip ( SoC ) and develop innovative ASIC solutions for...with components for stimulus, checkers, and reference models 18. Block/IP/ SoC /full chip level verification 19. Formal property… more
- Meta (Sunnyvale, CA)
- …close coverage with targeted Formal Verification Techniques at IP, Subsystem and SoC level 5. Build reusable/scalable environments for Formal Verification and ... **Summary:** Meta is hiring ASIC Formal Verification Engineer within the Infrastructure organization....with experience in Formal Verification to build IP and System On Chip ( SoC ) for data center… more
- NVIDIA (Santa Clara, CA)
- …teammate are huge plus + Experience in crafting test bench environments for unit and system level verification NVIDIA is widely considered to be one of the ... NVIDIA is seeking elite ASIC Verification Engineers to verify the design and...verify the design and implementation of the world's leading SoC 's and GPU's. This position offers the opportunity to… more
- Amazon (Cupertino, CA)
- …right trade-offs. Key job responsibilities - integrate multiple subsystems into top level SOC , ensure correct clock/reset/functional/DFT signal routing - As a ... help you develop into a better-rounded professional. Custom SoCs ( System on Chip) live at the heart of AWS...rapid integration of emergent technologies. We're looking for an ASIC Design Eengineer to help us trail-blaze new technologies… more
- NVIDIA (Santa Clara, CA)
- NVIDIA is seeking best-in-class ASIC Design Engineers to design and implement the world's leading SoC 's and GPU's. This position offers the opportunity to have ... Design team, you will be responsible for the implementation of GPU sub- system modules. + Make architectural trade-offs based on features, performance requirements… more
- NVIDIA (Santa Clara, CA)
- …Engineer. NVIDIA is seeking ASIC Design Engineers to implement the world's leading SoC 's and GPU's. This position offers the opportunity to have real impact in a ... + Analyze architectural trade-offs based on features, performance requirements and system limitations. + Craft micro-architecture, implement in RTL, and deliver a… more
- NVIDIA (Santa Clara, CA)
- …a background in high-speed coherent interconnects, protocol bridges, hardware-managed coherency and system level caches. + Experience with multiple clock domains ... NVIDIA is looking for a Senior ASIC Design Engineer to join our Memory Subsystem...verification/physical design team to deliver a world-class solution. NVIDIA SOC Interconnects are among the industry's most sophisticated because… more
- Google (Sunnyvale, CA)
- …in modeling and optimizing chip power, as well as have an understanding of system level power considerations and tradeoffs. The AI and Infrastructure team is ... + 5 years of experience in logic design, digital ASIC , or SoC design. + Experience with...system levels (including DVFS, Turboing, Thermal Management, and system - level tradeoffs). + Ability to solve open-ended… more
- Microsoft Corporation (Santa Clara, CA)
- …verification strategies and test plans. Owns verification of complex flows at the system on chip ( SoC ), subsystem (SS), or intellectual property (IP) levels. ... changes and provide quantitative justification. Leads verification of correlation of system on chip ( SoC ) performance models to RTL implementation.… more
- NVIDIA (Santa Clara, CA)
- NVIDIA is seeking ASIC Design Engineers to implement the world's leading SoC 's and GPU's. This position offers the opportunity to have real impact in a ... + Analyze architectural trade-offs based on features, performance requirements and system limitations. + Craft micro-architecture, implement in RTL, and deliver a… more