We interpreted Mountain View, CA as Mountain View, CA. Other options include: Mountain View (Contra Costa County), CA

  • ASIC DFT Verification

    Cisco (San Jose, CA)
    …You'll Work With: You will be in the Silicon One development organization as a senior DFT verification lead in San Jose, CA. You will work with Front-end RTL ... physical design teams to understand chip architecture and drive high-quality DFT verification . What You'll Do: * Responsible for thorough test planning and… more
    Cisco (04/18/25)
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  • ASIC Engineering Technical Lead-…

    Cisco (San Jose, CA)
    …industry. Your Impact: You will be in the Silicon One development organization as an ASIC Implementation Technical Lead in San Jose, CA with a primary focus on ... developing custom DFT logic & IP integration; familiarity with functional verification Preferred Qualification: * DFT CAD development - Test Architecture,… more
    Cisco (02/18/25)
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  • ASIC Implementation Engineer - Static…

    Meta (Sunnyvale, CA)
    …on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Implementation Engineer - Static Verification Responsibilities: 1. Perform Flat ... **Summary:** Meta is hiring ASIC Frontend Implementation Engineers within our Infrastructure organization....with the Designers to create waivers. 4. Perform RTL DFT Analysis and improve the DFT coverage… more
    Meta (04/04/25)
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  • ASIC Design Technical Leader…

    Cisco (San Jose, CA)
    …service provider networks. Cisco's silicon team provides a unique experience for ASIC engineers by combining the resources offered by a large multi-geography silicon ... breadth of growth opportunities that working in a smaller ASIC team can provide. You will work with exceptional...oversees fullchip SDCs and works with physical design and DFT teams to close fullchip timing in multiple timing… more
    Cisco (05/02/25)
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  • ASIC Engineering Technical Leader…

    Cisco (San Jose, CA)
    …service provider networks. Cisco's silicon team provides a unique experience for ASIC engineers by combining the resources offered by a large multi-geography silicon ... breadth of growth opportunities that working in a smaller ASIC team can provide. You will work with exceptional...fullchip SDCs and work with the Physical Design and DFT teams to close fullchip timing in multiple timing… more
    Cisco (04/02/25)
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  • ASIC Engineering Technical Leader…

    Cisco (San Jose, CA)
    …* Help define, evolve, and support our design methodology. * Collaborate with the verification , PD, DFT , Package and SW teams to develop next generation ASICs. ... will engage in dynamic collaboration with Senior micro-architects, designers, verification engineers and interact with cross-functional software and product teams,… more
    Cisco (03/08/25)
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  • ASIC Implementation Engineer - Synthesis

    Meta (Sunnyvale, CA)
    **Summary:** Meta is hiring ASIC Implementation Engineers within our Infrastructure organization. We are looking for individuals with experience in front-end ... Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Implementation Engineer - Synthesis Responsibilities: 1. Run Logic/Physical Synthesis using… more
    Meta (04/18/25)
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  • ASIC Implementation Engineer - Synthesis

    Meta (Sunnyvale, CA)
    **Summary:** Meta is hiring ASIC Implementation Engineers within our Infrastructure organization. We are looking for individuals with experience in front-end ... Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Implementation Engineer - Synthesis Responsibilities: 1. Run Logic/Physical Synthesis using… more
    Meta (04/16/25)
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  • Principal Custom ASIC Engineering Lead

    Broadcom (San Jose, CA)
    …Logic design, chip architecture, microarchitecture, Verilog RTL coding Front-end logic design verification , DRC, logic synthesis + Knowledge of DFT methods ... please Sign-In before you apply.** **Job Description:** **Senior Custom ASIC Engineering Lead** Are you a versatile, senior engineer...cross-functional teams in areas such as physical design, STA, DFT , and packaging? Have you taped out so many… more
    Broadcom (02/21/25)
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  • ASIC Design Engineer, Cloud-Scale Machine…

    Amazon (Cupertino, CA)
    …Our custom chips, accelerators, and software stacks enable us to take on technical challenges that have never been seen before, and deliver results that help ... scale and rapid integration of emergent technologies. We're looking for an ASIC Design Eengineer to help us trail-blaze new technologies and architectures, while… more
    Amazon (04/23/25)
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  • ASIC Physical Design Engineer Intern,…

    Amazon (Cupertino, CA)
    …distribution, timing optimization, place and route, power integrity analysis, and physical verification * Write Tcl or PERL scripts to improve physical design flows ... and methods * Collaborate with RTL, DFT designers to ensure high quality design implementation Basic Qualifications - Enrolled in a Bachelors' degree program or… more
    Amazon (04/04/25)
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  • Semiconductor Reliability Engineer

    Cisco (San Jose, CA)
    …partner organizations such as the Corporate Hardware Group to bring complex Cisco ASIC & Switch products to market. You will also engage closely with engineering ... bring-up and diagnostics teams, test & verification teams, and Product Quality teams to identify and...the NPI or Production processes. Your Impact As a Technical Leader in Silicon Reliability, you will play a… more
    Cisco (04/16/25)
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  • Circuits Design Engineer, Clock Design, University…

    Google (Sunnyvale, CA)
    verification , and signoff. Preferred qualifications: + Experience in ASIC physical design, physical design flows, and methodologies including synthesis, place ... and route, Static Timing Analysis (STA), formal verification , Change Data Capture (CDC), and power analysis. +...Design you will collaborate with the architecture, logic design DFT , physical design, and circuits/technology teams to overcome the… more
    Google (03/04/25)
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  • Sr. Physical Design Methodology Engineer,…

    Amazon (Cupertino, CA)
    …Our custom chips, accelerators, and software stacks enable us to take on technical challenges that have never been seen before, and deliver results that help ... scale and rapid integration of emergent technologies. We're looking for an ASIC Physical Design Methodology Engineer to help us trail-blaze new technologies and… more
    Amazon (03/29/25)
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  • Physical Design Engineer, Static Timing Analysis

    Google (Sunnyvale, CA)
    …degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field, or equivalent practical experience. + 7 years of experience ... static timing (ie, full chip timing signoff ownership, constraint authoring and verification , full chip static timing analysis and timing ECO creation, timing… more
    Google (04/23/25)
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  • Circuit Design And Analysis, Annapurna Labs, Cloud…

    Amazon (Cupertino, CA)
    …Design from RTL-to-GDSII - Understanding of other sign-off activities (ir/em, physical verification , timing closure, DFT ) - 3+ years of scripting experience ... Amazon's leadership principles requirements for this role - Meets/exceeds Amazon's functional/ technical depth and complexity for this role Amazon is an equal… more
    Amazon (03/21/25)
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