We interpreted Mountain View, CA as Mountain View, CA. Other options include: Mountain View (Contra Costa County), CA
- Meta (Sunnyvale, CA)
- **Summary:** Meta is hiring ASIC Formal Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in ... Post-Silicon teams towards creating a first-pass silicon success. **Required Skills:** ASIC Engineer , Formal Verification Responsibilities: 1. Provide… more
- Meta (Sunnyvale, CA)
- **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in ... teams towards creating a first-pass silicon success. **Required Skills:** ASIC Engineer , Design Verification Responsibilities:...or more of the following areas along with functional verification - SV Assertions, Formal , Emulation 20.… more
- Meta (Sunnyvale, CA)
- **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in ... and Post-Silicon teams towards creating a first-pass silicon success. **Required Skills:** ASIC Engineer , Design Verification Responsibilities: 1. Define and… more
- Meta (Sunnyvale, CA)
- **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in ... and Post-Silicon teams towards creating a first-pass silicon success. **Required Skills:** ASIC Engineer , Design Verification Responsibilities: 1. Define and… more
- Qualcomm (Santa Clara, CA)
- …such as SystemVerilog-UVM, coverage development, assertion model development and formal verification (property checking). Learn and deploy power-aware ... closely related field + 2+ years of experience with ASIC design and verification tools, techniques, and...as UVM or OVM and exposure to Assertion based Formal Verification + 3+ years of experience… more
- Cisco (San Jose, CA)
- ASIC Verification Engineer Apply (https://jobs.cisco.com/jobs/Login?projectId=1431425) + Location:San Jose, California, US + Area of InterestEngineer - ... Verilog / UVM programming + 4+ Years post graduate ASIC Verification processes, methodologies, flows and tools...Understanding of Networking technologies and concepts + Experience with Formal verification + Experience with Post-silicon lab… more
- Cisco (San Jose, CA)
- ASIC Design Verification Engineer Apply...MMU. + Experience with Veloce/HAPS is a plus + Formal verification (iev/vc formal ) knowledge is ... Work With:** You will be in the Silicon One development organization as an ASIC design verification engineer in San Jose, CA. You collaborate closely with … more
- Cisco (San Jose, CA)
- Senior ASIC Design Verification Engineer Apply (https://jobs.cisco.com/jobs/Login?projectId=1444077) + Location:San Jose, California, US + Area of ... in the industry. **Your Impact** + Participate in the ASIC design verification for Cisco high-end switching...and/or Python/Perl. + Experience in Networking. + Experience with Formal verification . **Why Cisco?** At Cisco, we're… more
- NVIDIA (Santa Clara, CA)
- The NVIDIA Clocks Team is looking for an excellent Senior ASIC Verification engineer with extensive experience in Design Verification . The NVIDIA Clocks ... reset logic to various units in SOC and GPU ASIC . The complexity of the clocks and resets design...industry-standard verification flows like SV constraint random verification , UVM, Formal Verification , Coverage… more
- NVIDIA (Santa Clara, CA)
- NVIDIA is seeking a hardworking Senior ASIC Design Verification Engineer to help drive sign-off strategies for world's leading GPUs and SoCs. This position ... silicon correlation. + Own the unit and sub-system level verification of various IPs, create functional test plans, and...as VCS-XA or equivalent tools, Gate Level Simulation or Formal Equivalence domains. + Proficiency in scripting language, such… more
- Amazon (Sunnyvale, CA)
- …in the validation of ASIC implementations in Verilog/SystemVerilog . Run formal verification of complex blocks to ensure functional correctness . Work ... Matlab model : development or DV integration experience - Familiarity with formal verification techniques - Strong written and verbal skills Amazon is an equal… more
- Amazon (Sunnyvale, CA)
- …digital verification , preferably in areas of image processing. - Familiarity with formal verification techniques - Lab debug experience and/or FPGA debug - ... highly differentiated silicon into Blink and Ring battery powered devices. Our verification team works on state-of-the art SoCs in a vertically integrated team… more
- Palo Alto Networks (Santa Clara, CA)
- …silicon validation and lab bring-up experience **.** **Preferred / Nice-to-Have** + Formal verification ownership and expertise. + Experience with innovation or ... we all win with precision. **Your Career** Join our ASIC team and help deliver the digital logic that...powers our next-generation firewall platforms. As a Senior Principal Engineer , you will take end-to-end ownership of complex modules… more
- Cisco (San Jose, CA)
- …concepts + Scripting experience (Python, Perl, TCL, shell programming) + Experience with formal verification tools + Experience with emulation **Why Cisco?** At ... Senior ASIC Design Engineer Apply (https://jobs.cisco.com/jobs/Login?projectId=1443694) +...and support our design methodology. + Collaborate with the verification team to address design bugs and close code… more
- Cisco (San Jose, CA)
- …aspects of our systems, leveraging the latest technology. We're seeking a talented ASIC engineer with a proven track record in high-performance products, ready ... ASIC Design Engineer - Design &...with Spyglass CDC and glitch analysis + Experience using Formal Verification : Synopsys Formality and Cadence LEC.… more
- Amazon (Sunnyvale, CA)
- … development in a production setting - Experience with UVM - Familiarity with formal verification techniques - Familiarity with the TCL programming language - ... Astro personal robot. What will you help us create? As an ASIC Methodology / CAD engineer you will create and maintain automated design flows that improve the… more
- Broadcom (San Jose, CA)
- …* Synthesis using Synopsys tool suite * Timing Analysis using Synopsys Primetime tool * Formal Verification * DFT concepts of Scan, BIST. * Strong Perl and Tcl ... challenged and gain valuable experience towards enhancing a successful career in ASIC design. You will involve in engineering implementation spec writing from… more
- NVIDIA (Santa Clara, CA)
- NVIDIA is looking for an ASIC Design Engineer to join our Global Circuits Team! In this position, you'll make a real impact in a dynamic, technology-focused ... and the latest process technologies. + Work on functional verification , perform CDC checks and formal equivalence....ASIC design flow including front end design and verification , DFT, timing analysis, ECO, ATE test development, post-si… more
- Cisco (San Jose, CA)
- …Cadence) + Experience with Spyglass CDC and glitch analysis + Experience using Formal Verification : Synopsys Formality and Cadence LEC. + Experience with ... ASIC Design Technical Leader - Design & Timing...customer shipments **Your Impact** You are a diligent Design/SDC Engineer with strong analytical skills and a deep understanding… more
- Amazon (Sunnyvale, CA)
- …methodology - Develop, regress and deploy digital implementation flows including Synthesis and Formal Verification - Enable digital design teams to meet PPA ... Come work at Amazon! The Role: As Senior CAD Engineer you will be responsible for installing and maintaining...and debugging techniques - Familiar with basic Synthesis and Formal Verification methodology and flow development experience… more