We interpreted Mountain View, CA as Mountain View, CA. Other options include: Mountain View (Contra Costa County), CA
- Cisco (San Jose, CA)
- **Sr. ASIC Engineer ** The application window is expected to close on 1/26/2026. The job posting may be removed earlier if the position is filled or if a ... year of ASIC experience. + Experience with microarchitecture and RTL implementation . + Experience with block/full chip SDC development in functional and test… more
- SpaceX (Sunnyvale, CA)
- …world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation ). In this role, you will be ... Sr. SOC/ ASIC Physical Design Engineer (Silicon Engineering)...Develop/improve physical design methodologies and automation scripts for various implementation steps + Closely collaborate with the ASIC… more
- Meta (Sunnyvale, CA)
- …apply, click "Apply to Job" online on this web page. **Required Skills:** ASIC Engineer , Implementation Responsibilities: 1. Run logic/physical synthesis ... Physical Design Execution for Clock Tree Synthesis and Routing optimization 19. 4 Static timing analysis and verification at different PVT corner 20. 5. Timing ECO… more
- Meta (Sunnyvale, CA)
- …System on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Engineer , Physical Design Responsibilities: 1. Develop and own physical ... **Summary:** Meta is hiring ASIC Physical Design Engineers within our Infrastructure organization....We are looking for individuals with experience in backend implementation from Netlist to GDSII in low power and… more
- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you want ... full chip level. + Help in driving frontend and backend implementation including synthesis, equivalence checking, floor-planning, timing constraints, timing and… more
- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you want ... full chip level. + Help in driving frontend and backend implementation including synthesis, equivalence checking, floor-planning, timing constraints, timing and… more
- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you want ... timing constraints, driving timing and power convergence, as well as ECO implementation + Apply knowledge and experience to improve timing convergence flows working… more
- NVIDIA (Santa Clara, CA)
- …amplify human inventiveness and intelligence. We are now looking for a motivated Senior ASIC Physical Design Engineer , Netlisting to join our dynamic and growing ... timing convergence, timing constraints generation and management, and ECO generation and implementation . What we need to see: + BS (or equivalent experience) in… more
- Google (Sunnyvale, CA)
- Senior DFT Static Timing Analysis Engineer , Cloud _corporate_fare_ Google _place_ Sunnyvale, CA, USA **Mid** Experience driving progress, solving problems, and ... AI/ML-driven systems. In this role, you will work on the physical implementation of Application-specific integrated circuits ( ASIC ) using advanced technology… more
- SpaceX (Sunnyvale, CA)
- …world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation ). In this role, you will be ... Sr. Full Chip Physical Design Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was...for testability (DFT) planning + Collaborate with chip architects, ASIC engineers, package engineers and block level physical design… more
- Broadcom (San Jose, CA)
- …plan. 5). Develop Verilog RTL. design verification support, logic synthesis, physical implementation constraints, static timing analysis. 6). Work directly with ... Group at Broadcom has brought some of the most complex and cutting-edge networking ASIC 's and multichip solutions to market over the last decade. The group develops … more
- Cadence Design Systems, Inc. (San Jose, CA)
- …to make an impact on the world of technology. Job Title: Lead Application Engineer Location: Tampere, Finland Reports to: AE Director Job Overview: This Digital IC ... support role offers an opportunity to work on a variety of digital implementation and support activities associated with Cadence EDA tools for Synthesis, Logical… more
- Meta (Sunnyvale, CA)
- **Summary:** As a Digital Design Engineer at Meta Reality Labs, you will work with a industry-leading group of researchers and engineers, and use your digital design ... drive our industry leading wearable systems. **Required Skills:** Digital Design Engineer Responsibilities: 1. Responsible for top-level or block level uArchitecture… more
- Meta (Sunnyvale, CA)
- **Summary:** As a Digital Design Engineer at Meta Reality Labs, you will work with a world-class group of researchers and engineers, and use your digital design ... virtual and augmented reality systems. **Required Skills:** Digital Design Engineer Responsibilities: 1. Responsible for top-level or block level uArchitecture… more
- Broadcom (San Jose, CA)
- …you apply.** **Job Description:** Broadcom is looking for a senior level STA engineer . In this highly visible role, you will be contributing to highly integrated ... Develop and validate timing constraints for intricate SoC designs. + Perform static timing analysis (STA) using industry-standard tools (eg, PrimeTime, Tempus). +… more