We interpreted Mountain View, CA as Mountain View, CA. Other options include: Mountain View (Contra Costa County), CA
- Meta (Sunnyvale, CA)
- …on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Implementation Engineer - Timing Responsibilities: 1. Develop Timing ... **Summary:** Meta is hiring ASIC Frontend Implementation Engineers within our...and the top-level including SOC. 2. Analyze the inter-block timing and come up with IO budgets for the… more
- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If ... timing and power convergence, as well as ECO implementation + Apply knowledge and experience to improve ...implementation + Apply knowledge and experience to improve timing convergence flows working with the methodology teams. What… more
- NVIDIA (Santa Clara, CA)
- …for all aspects of timing including setting up timing constraints, timing analysis and closure, ECO implementation , and timing methodologies. + ... MS (or equivalent experience) with 3+ years' experience in ASIC Design and Timing + Hands-on experience...Timing + Hands-on experience in STA tools, ECO implementation , and timing closure of high-speed designs.… more
- Meta (Sunnyvale, CA)
- …System on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Implementation Engineer - Synthesis Responsibilities: 1. Run ... **Summary:** Meta is hiring ASIC Implementation Engineers within our Infrastructure...optimization techniques and generate optimized Gate Level Netlist for Timing , Area, Power. 2. Debug the timing /area/congestion… more
- Meta (Sunnyvale, CA)
- …System on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Implementation Engineer - Synthesis Responsibilities: 1. Run ... **Summary:** Meta is hiring ASIC Implementation Engineers within our Infrastructure...optimization techniques and generate optimized Gate Level Netlist for Timing , Area, Power. 2. Debug the timing /area/congestion… more
- Meta (Sunnyvale, CA)
- …System on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Implementation Engineer - Static Verification Responsibilities: 1. ... **Summary:** Meta is hiring ASIC Frontend Implementation Engineers within our...Qualifications: 16. Experience with SOC Design Integration and Front-End Implementation . 17. Knowledge of Timing /physical libraries, SRAM… more
- Broadcom (San Jose, CA)
- …major segments of the Semiconductor industry, including AI. Be part of the Design Implementation team within Broadcom ASIC Products Division where we create CMOS ... concept through product release. Become a member of an ASIC design team responsible for all aspects of physical...- Floor planning chips and blocks - Routing - Timing , both mission mode and test modes - Integration… more
- Amazon (Sunnyvale, CA)
- …Engineering or related field, or equivalent experience. * 7+ years of experience in ASIC implementation , ie, synthesis, STA and working with P&R for deep ... and DFT teams to understand the design and create timing constraints. * Check the RTL design for clean.../ Communications Engineering. * 10+ years of experience in ASIC implementation . * Experience in leading physical… more
- Meta (Sunnyvale, CA)
- …apply, click "Apply to Job" online on this web page. **Required Skills:** ASIC Engineer , Implementation Responsibilities: 1. Run logic/physical synthesis ... optimization techniques and generate optimized gate level netlist for Timing , Area, and Power. 2. Debug timing /area/congestion...for Timing , Area, and Power. 2. Debug timing /area/congestion issues and resolve w/ RTL & physical designers.… more
- SpaceX (Sunnyvale, CA)
- …world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation ). In this role, you will be ... Sr. SOC/ ASIC Physical Design Engineer (Silicon Engineering)...Develop/improve physical design methodologies and automation scripts for various implementation steps + Closely collaborate with the ASIC… more
- Cisco (San Jose, CA)
- …service provider networks. Cisco's silicon team provides a unique experience for ASIC engineers by combining the resources offered by a large multi-geography silicon ... breadth of growth opportunities that working in a smaller ASIC team can provide. You will work with exceptional...customer shipments. Your Impact You are a diligent Design/SDC Engineer with strong analytical skills and a deep understanding… more
- Palo Alto Networks (Santa Clara, CA)
- …to create an environment where we all win with precision. **Your Career** As a Design engineer on the ASIC team, you will create complex digital logic for our ... goals for area, timing , power, and testability in close collaboration with ASIC physical design engineers + Perform synthesis + Optimize floorplan + Analyze and… more
- Meta (Sunnyvale, CA)
- …System on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Engineer , Physical Design Responsibilities: 1. Develop and own physical ... **Summary:** Meta is hiring ASIC Physical Design Engineers within our Infrastructure organization....We are looking for individuals with experience in backend implementation from Netlist to GDSII in low power and… more
- NVIDIA (Santa Clara, CA)
- NVIDIA is looking for an ASIC Design Engineer to join our Memory Subsystem Team! As an ASIC Design engineer at NVIDIA, you'll join a group of ... you will be responsible for the micro-architecture and design implementation of Tegra SOC memory subsystem modules. You will...a plus. + Experience with all stages in the ASIC design flow including emulation, prototyping, DFT, timing… more
- Meta (Sunnyvale, CA)
- …complex SoC and IP for data center applications. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Architecture exploration 2. Micro-architecture ... **Summary:** Meta is hiring ASIC Design Engineers within our Infrastructure organization to...in test plan development and debug 7. Collaboration with implementation team to close the design on timing… more
- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Physical Design Engineer to join our dynamic and growing team. If ... and GPUs. + Explore design space, create optimum floorplan, drive synthesis, physical implementation , and timing closure by understanding arch/logic as well as… more
- Broadcom (San Jose, CA)
- …be challenged and gain valuable experience towards enhancing a successful career in ASIC design. You will involve in engineering implementation spec writing from ... marketing/system requirements, RTL design and verification, synthesis, static timing analysis. You will either be responsible for block and/or chip level design and… more
- Meta (Sunnyvale, CA)
- …complex SoC and IP for data center applications. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Micro-architecture development. 2. RTL ... **Summary:** Meta is hiring ASIC Design Engineers within our Infrastructure organization to...in test plan development and debug. 6. Collaboration with implementation team to close the design on timing… more
- Meta (Sunnyvale, CA)
- …complex SoC and IP for data center applications. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Architecture exploration 2. Micro-architecture ... **Summary:** Meta is hiring ASIC Design Engineers within our Infrastructure organization to...in test plan development and debug 6. Collaboration with implementation team to close the design on timing… more
- Meta (Sunnyvale, CA)
- …complex SoC and IP for data center applications. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Architecture exploration. 2. Micro-architecture ... **Summary:** Meta is hiring ASIC Design Engineers within our Infrastructure organization to...in test plan development and debug. 5. Collaboration with implementation team to close the design on timing… more