We interpreted Mountain View, CA as Mountain View, CA. Other options include: Mountain View (Contra Costa County), CA
- Google (Sunnyvale, CA)
- …measuring chip power consumption. + Develop design improvements to increase power efficiency . + Collaborate with cross-functional teams in defining power ... using EDA tools such as PTPX, PowerArtist, or PrimePower. + Experience driving power - efficiency improvement in chip designs. + Experience with pre-silicon vs… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior ASIC Power Engineer ! NVIDIA is seeking extraordinary power engineers to design hardware accelerators and processors on ... to extend the state of the art performance and efficiency + You are expected to understand the design...are expected to understand the design and implementation, develop power metrics and drive power reductions +… more
- Google (Sunnyvale, CA)
- …experience with System Level Test or System validation. + Experience with ASIC or SoC prototype bring-up, debug, functional verification, or functional manufacturing ... process, Kernel, and CPU performance. + Experience implementing secure ASIC /SoC manufacturing solutions (provisioning, e-fuse programming, or life-cycle management).… more
- Qualcomm (Santa Clara, CA)
- …of the position involves comprehensive pre-silicon test planning for digital power IP's, its testbench development using the advanced verification methodology such ... model development and formal verification (property checking). Learn and deploy power -aware UPF verification flow and methodology. Involve in developing automation… more
- NVIDIA (Santa Clara, CA)
- …Design Verification Engineers with a specialty in tools and automation to drive efficiency and collaboration among our High Speed IO engineering teams. This position ... of relevant industry experience + Exposure to computer architecture, ASIC design, and verification methodology is required + Experience...the challenge of crafting the highest performance & lowest power silicon possible? If so, we want to hear… more
- Google (Mountain View, CA)
- …+ Experience with logic synthesis techniques to improve RTL code, performance and power as well as low- power design techniques. + Experience with ARM-based ... SoCs, interconnects and ASIC methodology. + Experience with a scripting language like...interconnects or peripherals. + Experience with methodologies for low power estimation, timing closure, or synthesis. + Experience with… more
- Google (Sunnyvale, CA)
- …specific focus on TPU architecture and its integration within AI/ML-driven systems. As an ASIC Design Verification Engineer , you will be part of a team ... team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to...use Google services around the world. We prioritize security, efficiency , and reliability across everything we do - from… more
- Google (Mountain View, CA)
- …like Python or Perl. + Experience with ARM-based SoCs, interconnects and ASIC methodology. Preferred qualifications: + Master's degree or PhD in Electrical ... industry experience with IP design. + Experience with methodologies for low power estimation, timing closure, synthesis. + Experience with methodologies for RTL… more
- Google (Sunnyvale, CA)
- …ASICs. + Experience in memory subsystem design verification. + Experience in Power aware verification, Gate level simulations, and Post silicon bring-up. + ... Familiarity with ASIC standard interfaces and memory system architecture. In this...team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to… more
- Broadcom (San Jose, CA)
- …high throughput Ethernet solutions that deliver unprecedented performance at critically important power efficiency ._** **_We are looking for highly skilled and ... efficient Constrained Random Design Verification engineers that want to verify new designs that can evolve rapidly at every generation in a very dynamic market using industry proven methodologies using System Verilog and UVM. You can become a member of an… more
- NVIDIA (Santa Clara, CA)
- …power data, and driving ASIC teams to improve their units' power efficiency ; and is responsible for researching, developing, and deploying methodologies ... We are now looking for a Senior Power Architecture and Optimization Engineer ! NVIDIA... power analysis tools, to help improve product power efficiency . + Develop and share best… more
- NVIDIA (Santa Clara, CA)
- …power data and driving ASIC teams to improve their units' power efficiency ; and is responsible for researching, developing, and deploying methodologies to ... We are looking for a Senior Emulation Power Engineer ! NVIDIA prides in having...concepts of energy consumption, estimation, data movement and low power design. + Familiarity with Verilog and ASIC… more
- NVIDIA (Santa Clara, CA)
- …pre-silicon gate-level and RTL power analysis tools, to help improve product power efficiency . + Develop and share best practices for performing pre-silicon ... We are now looking for a Power Architecture and Optimization Engineer -...concepts of energy consumption, estimation, data movement and low power design. + Familiarity with Verilog and ASIC… more
- NVIDIA (Santa Clara, CA)
- …a trailblazer at the forefront of graphics and artificial intelligence performance, efficiency , and innovation. From our roots as a groundbreaking graphics company, ... industries. NVIDIA Silicon Solutions Group is seeking a versatile engineer to be part of the HW ArchDev team....Build roadmaps of system level features to address low power , low noise, perf/watt efficient product needs by doing… more
- Google (Sunnyvale, CA)
- …unparalleled performance, efficiency , and integration. As a System Level Test Engineer , you'll help to integrate System on Chip (SoC) technologies into High ... practical experience. + Experience with hardware testing of systems based on custom ASIC 's or SoC products + Experience with Linux/Unix, Python programming, or basic… more
- Qualcomm (Santa Clara, CA)
- …**General Summary:** As a Design Verification Lead, you will lead a team of ASIC design verification engineers to verify IP and Subsystems that be integrated in a ... validation and design teams to verify IP that meets power , performance and area goals for Qualcomm Wireless and...debugs + Build, manage and mentor a team of ASIC DV engineers + Explore innovative DV methodologies (formal,… more
- Palo Alto Networks (Santa Clara, CA)
- …integrity analysis of ASIC and multi-chip-module designs + Model and analyze power delivery networks for ASIC /package/module and PCB + Create SI test plan ... Experience** + Strong background in hands-on design and validation of high-speed PCB and ASIC package development + Power integrity design and analysis and well… more
- Qualcomm (Santa Clara, CA)
- …is the Invention Age - and this is where you come in as an ASIC Design Verification Engineer The team is responsible for the complete verification lifecycle, ... of the position involves comprehensive pre-silicon test planning for digital power IP's, its testbench development using the advanced verification methodology such… more
- Meta (Sunnyvale, CA)
- …Virtual Reality (VR) and Augmented Reality (AR). The compute performance and power efficiency requirements of Virtual and Augmented Reality require custom ... **Summary:** Meta's mission is to give people the power to build community and bring the world...learning accelerators and state-of-the-art SoCs. **Required Skills:** Digital Design Engineer Responsibilities: 1. Contribute to ASIC digital… more
- Google (Sunnyvale, CA)
- …will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency , and integration. As a Circuits Design Engineer , Clock ... clock verification, and signoff. Preferred qualifications: + Experience in ASIC physical design, physical design flows, and methodologies including synthesis,… more