We interpreted Mountain View, CA as Mountain View, CA. Other options include: Mountain View (Contra Costa County), CA
- Google (Sunnyvale, CA)
- …generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. As a Circuits Design Engineer , Clock Design ... in clock architecture and designing high speed clock distribution circuits . + Experience in Spice...power design techniques (eg, multi Vth/power/voltage domain design , clock gating, power gating, Dynamic Voltage… more
- Capgemini (San Jose, CA)
- …_Developer_ **Organization:** _ERD PPL US_ **Title:** _Senior E/E & Semiconductor Engineer - Mixed-Signal Design Verification Engineer_ **Location:** _CA-San ... **Job Role: Senior** **Mixed Signal DV Engineer ** **Job Location: San Jose CA** **Job description:**...This role will provide the ability to directly influence design related changes as required to meet functional specifications.… more
- NVIDIA (Santa Clara, CA)
- We are part of the global circuits team at NVIDIA that design the state-of-the-art GPUs for all applications such as supercomputers, gaming consoles and self ... driving cars. Come join us in our mission to Engineer the next generation of best-in-class products. Our teams...Design Engineering + Familiar with aspects of chip design including Floor planning, Clock and Power… more
- NVIDIA (Santa Clara, CA)
- …amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Physical Design Engineer to join our dynamic and growing team. If you want ... What you'll be doing: + Drive next generation physical design work to achieve best in class PPA for...and methods/techniques to address those. + Understanding of high-speed clock distribution and planning as well as impact of… more
- Cisco (San Jose, CA)
- …As a Technical Leader, you will be responsible for overseeing the design and verification of application-specific integrated circuits (ASICs), ensuring they ... PNR activities, from floor planning, bump and rdl planning, power grid design to clock planning, routing, and timing closure. * Perform full chip DRC/LVS/ERC/ANT… more
- NVIDIA (Santa Clara, CA)
- …experience in ASIC Design and Timing. + Good understanding of modeling circuits for sign-off + Good knowledge of extraction, device physics, STA methodology and ... intelligence. We are seeking an innovative Senior Timing Methodology Engineer to help drive sign-off strategies for the world's... design . + Clear understanding of low power design techniques such as multi VT, Clock … more