We interpreted Mountain View, CA as Mountain View, CA. Other options include: Mountain View (Contra Costa County), CA
- Qualcomm (Santa Clara, CA)
- …SoC Implementation Team is looking for skilled engineers to focus on timing constraints development, power analysis, STA , and timing closure for ... This is an excellent opportunity to join the Snapdragon implementation team, which is responsible for SoCs in sub-3nm...and low-power multi-voltage domain crossings, and signoff with static timing analysis. + Collaborate closely with RTL design… more
- Broadcom (San Jose, CA)
- … constraint development for hierarchical designs. + Knowledge of clock tree planning and implementation for SoCs. + Experience with timing ECO creation and final ... timing signoff. + Proficiency in using STA tools (eg, PrimeTime, Tempus) and scripting languages (eg,...Desired Qualifications: + Working with Genus tools (Cadence) for design synthesis including DFT flow, + Review timing… more
- Qualcomm (Santa Clara, CA)
- …you will work with microarchitecture and RTL design team to develop timing constraints, drive implementation of the designs to meet aggressive power, area ... Design Timing Engineer,... automation using TCL/Perl/Python. + Familiar with digital flow design implementation RTL to GDS : ICC, Innovous… more
- NVIDIA (Santa Clara, CA)
- …and/or full chip level. + Help in driving frontend and backend implementation including synthesis, equivalence checking, floor-planning, timing constraints, ... timing and power convergence, and ECO implementation . + Work in a cross-functional environment interacting with... Timing + Hands-on experience in full-chip/sub-chip Static Timing Analysis ( STA ), timing constraints… more
- NVIDIA (Santa Clara, CA)
- …in Physical design / Timing . + Experience in full-chip/sub-chip Static Timing Analysis ( STA ), timing constraints generation and management, and ... as timing constraints, timing analysis, timing convergence, and ECO implementation . What we...multiplexed scan logic and constraints. + Expertise in physical design , optimization, and ECO implementation eg cell… more
- NVIDIA (Santa Clara, CA)
- …or MS (or equivalent experience) with 3+ years' experience in ASIC Design and Timing + Hands-on experience in STA tools, ECO implementation , and ... timing including setting up timing constraints, timing analysis and closure, ECO implementation , and...to collaborate with cross-functional teams. + Strong understanding of timing and physical design fundamentals Ways to… more
- Meta (Sunnyvale, CA)
- …RTL DFT Analysis and improve the DFT coverage for Stuck-at faults. 7. Develop Timing Constraints for RTL-Synthesis and PrimeTime- STA for the blocks and the ... Methodology for all FE-tools including (Lint, CDC, RDC, Synthesis, STA , Power). 9. Work closely with the Design...supporting them with the handoff tasks. Interact with Physical Design Engineers and provide them with timing /congestion… more
- Qualcomm (Santa Clara, CA)
- …for all Qualcomm Business Units. Minimum Skill/Experience: + 2-10 yrs experience in Physical Design and timing signoff for high speed cores. + Should have good ... **Experience in leading block level or chip level Physical Design , STA and PDN activities** . +...Work independently in the areas of RTL to GDSII implementation . + Ability to collaborate and resolve issues wrt… more
- Meta (Sunnyvale, CA)
- …to develop reset groups and corresponding reset sequence for RDC. 10. Develop timing constraints for RTL-synthesis and PrimeTime- STA for blocks and top-level ... online on this web page. **Required Skills:** ASIC Engineer, Implementation Responsibilities: 1. Run logic/physical synthesis using advanced optimization techniques… more
- Meta (Sunnyvale, CA)
- …levels. From microarchitecture definition and RTL implementation to synthesis and timing closure, fundamentals in digital design will enable you to ... collaboration with Digital Verification (DV) 3. Support back end physical design (PD) through STA and SDCs 4. Drive IP/sub-system micro-architecture and RTL … more
- SpaceX (Sunnyvale, CA)
- …will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design , validation, product engineering, ASIC implementation ). In this ... voltage drop, logic equivalency and other signoff checks) + Develop/improve physical design methodologies and automation scripts for various implementation steps… more
- NVIDIA (Santa Clara, CA)
- …inventiveness and intelligence. What you will be doing: + Developing innovative physical design methodologies for implementation of GPU, CPU and SOCs, with ... tree synthesis methods and techniques + Strong background in STA , extraction, timing and RC correlation +...timing and RC correlation + Good understanding of design rules in advanced nodes and their impact on… more
- Broadcom (San Jose, CA)
- …with VLSI design tools for Place&Route, Verilog simulation, DRC/LVS verification, Timing analysis ( STA ), Scripting languages - Tcl?Perl/ Python + Proficiency ... ASICs. Key competencies required are: + Working experience in (digital) physical design implementation of large scale ASICs (Multi-100 million gates complexity).… more
- Google (Sunnyvale, CA)
- …related field, or equivalent practical experience. + 7 years of physical design experience with industry-standard tools, languages, and methodologies relevant to the ... of silicon-based ICs and chips. + Experience in logic synthesis, PnR, timing closure, and static timing analysis. Preferred qualifications: + Master's… more
- NVIDIA (Santa Clara, CA)
- …member of the DFX methodology team, you will be responsible for the architecture, design , implementation and verification of fuse controller and other DFT IPs ... architects, other designers, pre- and post-silicon verification teams, synthesis, timing and back-end teams + Work on generating test...exposure to cross functional areas including RTL & clocks design , STA , place-n-route and power, to ensure… more