We interpreted Mountain View, CA as Mountain View, CA. Other options include: Mountain View (Contra Costa County), CA
- NVIDIA (Santa Clara, CA)
- …integral part of the SOC Design team to develop and improve our RTL top - level assembly process and tool set + Top - level assembly: Test new ... The NVIDIA SOCD CAD team is looking for a top engineer with proven experience in hardware design...roadmap to address upcoming project challenges for top - level assembly + Create complex GPU, SOC ,… more
- NVIDIA (Santa Clara, CA)
- …) group is looking for a top ASIC Engineer with a curiosity about SOC design automation, RTL integration, chip build and assembly, and padring design ... We are looking for SOC Design Engineer! The complexity of...complex GPU and Tegra chips and interface, directly with unit- level ASIC, Physical Design , CAD, Package … more
- NVIDIA (Santa Clara, CA)
- …) group is looking for a top ASIC Engineer with a curiosity about SOC design automation, RTL integration, chip build and assembly, and padring design ... Are you looking for a SOC Design Engineer opportunity? If yes,...complex GPU and Tegra chips and interact directly with unit- level ASIC, Physical Design , CAD, Package … more
- Cadence Design Systems, Inc. (San Jose, CA)
- …using our components. The CSG Central Applications Engineering team seeks an experienced and talented SoC Design Manager to lead a new team for CSG systems. In ... Our IP designs are used by most of the top semiconductor vendors today, and our customers are shipping...will be responsible for managing a team of hardware design engineers to develop and validate reference systems for… more
- Meta (Sunnyvale, CA)
- …7+ years of experience as a Digital Design Engineer 10. Experience with top level integration using automation tools. 11. Experience in RTL coding, synthesis ... Digital Design Engineer Responsibilities: 1. Responsible for top - level or block level uArchitecture...and/or SoC Integration. 12. Experience in digital design … more
- Amazon (Cupertino, CA)
- …the right trade-offs. Key job responsibilities - integrate multiple subsystems into top level SOC , ensure correct clock/reset/functional/DFT signal routing ... Engineering or related technical field - 5+ years of experience in RTL design for SOC - 5+ years of experience VLSI engineering - 5+ years of experience… more
- NVIDIA (Santa Clara, CA)
- …C/C++ is essential. + Be familiar with hierarchical design approach, top -down design , SoC and system level verification. NVIDIA is on the move and ... Accelerated UVM Testbenches). + Bring up SOCs on emulation, root causing SoC /Processor test fails and emulator environment issues. + We have continual collaboration… more
- Cisco (San Jose, CA)
- …issues, provide solutions and ensure signoff clean results * Work with block and top level implementation teams to understand physical aspects and feedback on ... necessary updates * Work closely with block and TOP level physical implementation, IP development teams...with semiconductor foundries on installation, and maintenance of process design kits (PDKs) for SOC physical … more
- Cadence Design Systems, Inc. (San Jose, CA)
- …timing closure, power optimization, and physical verification for both of block and Chip top level You will also be responsible for interfacing with the Physical ... of technology. As a core member of the PHY Design team, your responsibilities will span across various aspects...teams in multiple successful ASIC/IP tapeouts. Knowledge of the IP/ SoC level timing closure flow and methodology.… more
- Meta (Sunnyvale, CA)
- …verification and UVM methodology. 10. 5+ years experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies. 11. ... and track detailed test plans for the different modules and top levels. 3. Drive Design Verification to closure based on defined verification metrics on test… more
- NVIDIA (Santa Clara, CA)
- …HSpice, Finesim, XA) + Experience in crafting test bench environments for component and top level circuit verification + Expertise in System Verilog or similar ... We are looking for an Engineer to verify the design and implementation of the world's leading SoC 's and GPU's. This position offers the opportunity to have real… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …emulation platform used for emulating complex custom silicon designs used by top semiconductor industries globally . The Palladium platform is a scalable emulation ... power devices into complex scalable enterprise grade hardware. The design / verification / physical design of...or Master's + Experience in RTL development of complex ASIC/ SoC . + Comfortable in Verilog and SystemVerilog for the… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …Palladium and Protium Emulation products to enable the critical shift-left of System Level SOC verification and Validation for Cadence customers. This position ... that combine a Virtual Machine running a production OS with the customer's SOC Design running on Candence's Palladium emulation or Protium Prototyping platforms.… more
- ManpowerGroup (Mountain View, CA)
- …excellent opportunity for a highly experienced hardware engineer to contribute to advanced SoC and block- level design in a collaborative, high-performance ... Power Intent and UPF Hardware Engineer** **Job Title: Hardware Design Engineer 5** **Location: Mountain View, CA (Onsite 1-2...as Prime Power, PP-RTL/Power Artist, Power Replay, and Empower. ** Top 3 Hard Skills Required + Years of Experience**… more
- Meta (Sunnyvale, CA)
- …generic compute units to custom silicon IP blocks, traditional compute benchmarking, and SOC and System level implications. The candidate will work with ... SOC IPs Power requirements including power states, high level power tree & power sequence requirements. 3. Work...of low power design principles across RTL, design and system level . **Preferred Qualifications:** Preferred… more
- Vector Atomic (Pleasanton, CA)
- …team of physicists, electronics engineers, and optical designers to define requirements and select FPGA/ SoC parts + Assist in the design of custom PCBs based on ... modern FPGA/ SoC devices + Identify and address critical design issues to ensure robust board layouts + Create RTL, test benches, and EDA support files to meet… more
- Meta (Sunnyvale, CA)
- …8. Develop Timing Constraints for RTL-Synthesis and PrimeTime-STA for the blocks and the top - level including SOC . Analyze the inter-block timing and come up ... CDC analysis, timing constraints, synthesis to build efficient System on Chip ( SoC ) and IP for data center applications. **Required Skills:** ASIC Engineer,… more
- Vector Atomic (Pleasanton, CA)
- …quantum instruments. + Code and verify system controllers on ARM SoC . Develop user-space drivers, data acquisition pipelines, and robust control loops ... + Experience in Python, including common scientific libraries + Design and coding of control algorithms such as PID....etc. + Experience in C/C++ + Background working with SoC /FPGA devices. + Experience with Linux device drivers. +… more
- Google (Mountain View, CA)
- …have: + MS Electrical Engineering or related field + Experience as a top - level chip owner and extensive tapeout experience including successful bring-up and ... Senior Integrated Circuit engineer leading the next generation circuit design as part of the R&D team developing cutting-edge...testing of mixed-signal SoC . + Demonstrated achievements in pushing the boundaries of… more
- Lightmatter (Mountain View, CA)
- …product. Work closely with the rest of the architecture team and the chip- design team. + Lead direct collaboration with top tier semiconductor customer(s) ... + Lead the development and drive methodologies and simulation workflows for electro-optic SoC co- design . + Collaborate with the product team to develop our… more