We interpreted Mountain View, CA as Mountain View, CA. Other options include: Mountain View (Contra Costa County), CA
- Qualcomm (Santa Clara, CA)
- … solutions which are setting benchmarks in the whole industry. As an SOC Verification and Methodology Engineer , you will be responsible for ensuring the ... and resolve design issues. In this role of Design Verification Engineer , you will be using advanced...verification skills & experience with assertion & coverage-based verification methodology + Knowledge of SOC… more
- Qualcomm (Santa Clara, CA)
- …based verification skills, experience with assertions, and coverage-based verification methodology + Strong leadership, Analytical and problem-solving skills ... complex IP blocks and subsystems. **Job Responsibilities** + Lead Sub-System & SoC Design verification for Qualcomm WIFI projects + Own end-end low power test… more
- NVIDIA (Santa Clara, CA)
- …to join us today! NVIDIA is looking for a SOC Design Methodologies Engineer with proven hardware design and methodology expertise to join our world-class ... safety/resiliency, and power-saving logic. + Act as a "DevOps" engineer for RTL automation by developing new features and...with Unix/Linux shell scripting and Makefiles. + Experience in verification , Perl, and compiler concepts is a plus. +… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …& route and signoff) and/or experience with functional and formal verification tools/ methodology , VIP. Understanding of semiconductor manufacturing eco-systems. ... the core technology requirements in the digital implementation and/or functional/formal verification space , coordination of sales strategies and efforts across… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior Design for Debug (DFD) Architect and Methodology Engineer ! NVIDIA is seeking a DFD Architect to implement hardware and software ... solutions to debug world's leading SoC 's and GPU's. This position offers the opportunity to...at NVIDIA. + Work closely with software, architecture, design, verification , and silicon validation teams. + Train and mentor… more
- Amazon (Sunnyvale, CA)
- …Echo, and the Astro personal robot. What will you help us create? As an ASIC Methodology / CAD engineer you will create and maintain automated design flows that ... ASIC products. Key job responsibilities - Develop automated flows for improving the SoC design process - Build robust, scalable tools that help verify and validate… more
- NVIDIA (Santa Clara, CA)
- …lasting impact on the world. We need a creative individual who understand ASIC and SoC test methodology , DFT techniques, NPI and ATE test program development and ... release. The individual will turn the test methodology into ATE test method library. efficient and user...experience in the semiconductor industry. + Knowledge of silicon verification , testing and manufacturing + Have knowledge in Advantest… more
- Meta (Sunnyvale, CA)
- …to build IP and System On Chip ( SoC ) for data center applications.As a Design Verification Engineer , you will be part of a dynamic team working with the best ... a first-pass silicon success. **Required Skills:** ASIC Engineer , Design Verification Responsibilities: 1. Define and implement IP/ SoC verification … more
- Meta (Sunnyvale, CA)
- …to build IP and System On Chip ( SoC ) for data center applications.As a Design Verification Engineer , you will be part of a dynamic team working with the best ... a first-pass silicon success. **Required Skills:** ASIC Engineer , Design Verification Responsibilities: 1. Define and implement IP/ SoC verification … more
- Meta (Sunnyvale, CA)
- …to build IP and System On Chip ( SoC ) for data center applications.As a Design Verification Engineer , you will be part of a dynamic team working with the best ... a first-pass silicon success. **Required Skills:** ASIC Engineer , Design Verification Responsibilities: 1. Define and implement block/IP/ SoC verification … more
- Qualcomm (Santa Clara, CA)
- …the Invention Age - and this is where you come in as an ASIC Design Verification Engineer The team is responsible for the complete verification lifecycle, ... for digital power IP's, its testbench development using the advanced verification methodology such as SystemVerilog-UVM, coverage development, assertion model… more
- Meta (Sunnyvale, CA)
- …protocols like PCIe/Ethernet/DDR, computer architecture and NOC. 4. Define and implement IP/ SoC verification plans, build verification test benches to ... Job" online on this web page. **Required Skills:** ASIC Engineer , Design Verification Responsibilities: 1. Evaluate, develop...enable IP/sub-system/ SoC level verification . 5. Develop functional tests based on … more
- Meta (Sunnyvale, CA)
- …to build IP and System On Chip ( SoC ) for data center applications. As a Formal Verification Engineer , you will be part of a team working with the best in the ... **Summary:** Meta is hiring ASIC Formal Verification Engineer within the Infrastructure organization....Verification 2. Propose, implement and evangelize the Formal Verification Methodology to be used across the… more
- Meta (Sunnyvale, CA)
- …the entire stack, through algorithms to architecture, transistors to firmware. As a Design Verification Engineer at Meta's Reality Labs, you will work with a ... multiple state of the art machine learning IPs. **Required Skills:** Design Verification Engineer - Machine Learning Accelerators Responsibilities: 1. Work with… more
- Meta (Sunnyvale, CA)
- …and UVM methodology . 9. 3+ years experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies. 10. Experience ... through architecture, to firmware, and algorithms. As a Design Verification Engineer at Meta Reality Labs, you...the testing infrastructure to validate new core IP or SoC implementations. You will work closely with researchers, architects… more
- Qualcomm (Santa Clara, CA)
- …Engineering Group, Engineering Group > CPU Engineering **General Summary:** As a Design Verification Engineer , you will work with Chip Architects to validate the ... concepts of CPU and SOC level micro-architectures. You will work on a selected...plans based on the Architecture and Micro-architecture. + Develop Verification Methodology , ensuring scalability and portability across… more
- Siemens (Fremont, CA)
- …Applications Engineer (AE) position delivers technical expertise for Functional Verification of digital, mixed-signal, and analog IC chip designs based on ... who like to interact with and influence others, possess strong design and/or verification background, requiring both in depth knowledge of HDL and HVL, as well… more
- Siemens (Fremont, CA)
- …Applications Engineer (AE) position delivers technical expertise for Functional Verification of digital, mixed-signal, and analog IC chip designs based on ... across a range of areas from application engineering support and management, verification and validation of complex semiconductor ICs, system testing, and beyond? If… more
- Meta (Sunnyvale, CA)
- …) and IP for data center applications. **Required Skills:** ASIC Implementation Engineer - Static Verification Responsibilities: 1. Perform Flat and Hierarchical ... for Timing, Area, Power. 6. Developing Automation scripts and Methodology for all FE-tools including (Lint, CDC, RDC,). 7....Minimum Qualifications: 8. 5+ years of experience in static verification tools 9. Experience with Lint, Clock Domain &… more
- Meta (Sunnyvale, CA)
- …and UVM methodology . 10. 5+ years experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies. 11. ... from transistor, through architecture, to firmware, and algorithms.As a Design Verification Engineer at Meta Reality Labs, you will work with a world-class… more