We interpreted Mountain View, CA as Mountain View, CA. Other options include: Mountain View (Contra Costa County), CA
- Arrow Electronics (San Jose, CA)
- **Position:** STA Engineer (eInfochips Inc) **Job Description:** **Position: STA Engineer (eInfochips Inc)** **Location: San Jose CA (Day-1 Onsite)** ... + Experience in **Static Timing Analysis** and prior working experience with STA tools like **PrimeTime/Tempus** + Understanding of related digital design concepts… more
- Broadcom (San Jose, CA)
- …please Sign-In before you apply.** **Job Description:** Broadcom is looking for a senior level STA engineer . In this highly visible role you will be working on ... with timing ECO creation and final timing signoff. + Proficiency in using STA tools (eg, PrimeTime, Tempus) and scripting languages (eg, Tcl, Perl). + Proficiency… more
- Qualcomm (Santa Clara, CA)
- …for skilled engineers to focus on timing constraints development, power analysis, STA , and timing closure for premium-tier chips. This is an excellent opportunity ... to join the Snapdragon implementation team, which is responsible for SoCs in sub-3nm nodes across mobile, AI, and automotive sectors. Candidates should have at least 2 years of experience and be proficient with tools such as Primetime, Fishtail/TCM. Scripting… more
- Qualcomm (Santa Clara, CA)
- …CPU timing closure for Oryon CPU Cores. As a CPU Physical Design Timing Engineer , you will work with microarchitecture and RTL design team to develop timing ... One of your primary responsibilities will lie in coding scripts used with STA native tools and also useful in enabling CPU timing infrastructure and methodology… more
- NVIDIA (Santa Clara, CA)
- …human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you want to challenge yourself ... or MS (or equivalent experience) with 2 years experience in Timing and STA + Hands-on experience in full-chip/sub-chip Static Timing Analysis ( STA ) and… more
- Qualcomm (Santa Clara, CA)
- …to help create a smarter, connected future for all. As a Qualcomm CPU Engineer , you will lead innovative Central Processing Unit (CPU) design efforts that have a ... in leading block level or chip level Physical Design, STA and PDN activities** . + Work independently in...to collaborate and resolve issues wrt constraints validation, verification, STA , Physical design, etc. + Knowledge of low power… more
- Meta (Sunnyvale, CA)
- …and IP for data center applications. **Required Skills:** ASIC Implementation Engineer - Synthesis Responsibilities: 1. Run Logic/Physical Synthesis using advanced ... coverage for Stuck-at faults. 7. Develop Timing Constraints for RTL-Synthesis and PrimeTime- STA for the blocks and the top-level including SOC. Analyze the… more
- NVIDIA (Santa Clara, CA)
- …inventiveness and intelligence. We are seeking a highly skilled Timing Methodology Engineer with expertise in asynchronous timing and I/O interface modeling to ... timing constraints, validating IO timing integrity, and enabling scalable STA methodologies across design hierarchies and technology nodes. We're looking… more
- Qualcomm (Santa Clara, CA)
- …proactively find solutions. This candidate will be working with Design, Synthesis and STA teams closely to provide physical design feedback and improve the overall ... in Floor Planning (FP), Placement, Clock Tree Synthesis (CTS), STA closure, and Physical verification closure for critical WiFi...is a must. - Debugging capability for PV and STA flows is preferred. - UPF knowledge is preferred.… more
- Meta (Sunnyvale, CA)
- **Summary:** We are looking for a Digital Design Engineer to support our Reality Labs Silicon AI Research team. We build research silicon to demonstrate and ... next generation AI and AR solutions.As a Digital Design Engineer (DDE), you will be a key contributor in...(DV) 3. Support back end physical design (PD) through STA and SDCs 4. Drive IP/sub-system micro-architecture and RTL… more
- Meta (Sunnyvale, CA)
- …for large complex disaggregated ASICs, with exposure to library characterization, STA , modeling, extraction, variation analysis, aging, and signoff flows to build ... Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Engineer , Methodology Responsibilities: 1. Work with our ASIC vendor partners and Foundries… more
- Amazon (Cupertino, CA)
- …AI services for our customers' businesses. We are seeking experienced Physical Design Engineer to build the next generation of our cloud server platforms. Our ... design, physical design flows, and methodologies including synthesis, place and route, STA , formal verification. - Proven track record of delivering metric driven… more
- NVIDIA (Santa Clara, CA)
- …human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you want to challenge yourself ... and Timing + Hands-on experience in full-chip/sub-chip Static Timing Analysis ( STA ), timing constraints generation and management, and timing convergence. +… more
- NVIDIA (Santa Clara, CA)
- …methodology on next generation CMOS technology. We are looking for a Senior ASIC Timing Engineer to join our dynamic and growing team! If you are problem solver and ... in Physical design/Timing. + Experience in full-chip/sub-chip Static Timing Analysis ( STA ), timing constraints generation and management, and timing convergence. +… more
- NVIDIA (Santa Clara, CA)
- …We are seeking an innovative senior timing signoff and constraint methodology engineer to develop pioneering timing sign-off strategies for next-generation GPUs and ... SNPS TCM ) and debug anomalies in timing reports. + Support tapeout-quality STA environments that are scalable, reusable, and validated through both structural and… more
- SpaceX (Sunnyvale, CA)
- SOC/ASIC Physical Design Engineer (Silicon Engineering) Sunnyvale, CA Apply SpaceX was founded under the belief that a future where humanity is out exploring the ... ultimate goal of enabling human life on Mars. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets… more
- Meta (Sunnyvale, CA)
- …to Job" online on this web page. **Required Skills:** ASIC Engineer , Implementation Responsibilities: 1. Run logic/physical synthesis using advanced optimization ... reset sequence for RDC. 10. Develop timing constraints for RTL-synthesis and PrimeTime- STA for blocks and top-level including SOC. 11. Analyze inter-block timing and… more
- Broadcom (San Jose, CA)
- …Candidate Account, please Sign-In before you apply.** **Job Description:** R&D Engineer position available in design and physical implementation of high performance ... design tools for Place&Route, Verilog simulation, DRC/LVS verification, Timing analysis ( STA ), Scripting languages - Tcl?Perl/ Python + Proficiency in UNIX/Linux… more
- Qualcomm (Santa Clara, CA)
- …push the envelope on performance, energy efficiency and scalability. As CPU EM/IR CAD engineer , you will build and support the world's best analysis tools and flows. ... user of Ansys Redhawk SC power integrity analysis toll and have exposure to PnR/ STA and extraction industry standard tools and flow + Support and enhance static IR,… more
- NVIDIA (Santa Clara, CA)
- …tools + Good exposure to cross functional areas including RTL & clocks design, STA , place-n-route and power, to ensure we are making the right trade-offs + ... world-class engineering teams are growing fast. If you're a creative and autonomous engineer with real passion for technology, we want to hear from you! #LI-Hybrid… more