We interpreted Mountain View, CA as Mountain View, CA. Other options include: Mountain View (Contra Costa County), CA
- Google (Sunnyvale, CA)
- …Science, a related field, or equivalent practical experience. + 5 years of experience in static timing analysis. + Experience in full chip timing sign-off ... ASICs. + Experience in PrimeTime or Tempus TCL scripting and static timing analysis debug. Preferred qualifications: + Experience writing, reviewing and… more
- NVIDIA (Santa Clara, CA)
- …design tradeoffs and methodology on next generation CMOS technology. We are looking for a Senior ASIC Timing Engineer to join our dynamic and growing team! ... experience in Physical design/ Timing . + Experience in full-chip/sub-chip Static Timing Analysis (STA), timing constraints generation and management, and… more
- NVIDIA (Santa Clara, CA)
- …to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you want to ... in Synthesis and Timing + Hands-on experience in full-chip/sub-chip Static Timing Analysis (STA), timing constraints generation and management, and … more
- NVIDIA (Santa Clara, CA)
- …to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you want to ... experience in Timing and STA + Hands-on experience in full-chip/sub-chip Static Timing Analysis (STA) and timing convergence, timing constraints… more
- NVIDIA (Santa Clara, CA)
- …or related field (or equivalent experience). + 6+ years of experience in static timing analysis, methodology, or constraint development. + Strong expertise in ... human inventiveness and intelligence. We are seeking a highly skilled Timing Methodology Engineer with expertise in asynchronous timing and I/O interface… more
- NVIDIA (Santa Clara, CA)
- …and graph databases, but it mostly requires a strong VLSI background in static timing , physical design, and related optimization techniques. Collaborating with ... thousands of times per day. We are seeking a Senior CAD Engineer excited to innovate in...Engineer excited to innovate in strategies for complex timing , power, and IR drop closure. The role will… more
- NVIDIA (Santa Clara, CA)
- …next generation of high-performance IPs for CPU, GPU and SOC designs. + Owning static timing analysis and convergence of high-performance designs. + You will be ... responsible for all aspects of timing including setting up timing constraints, timing analysis and closure, ECO implementation, and timing methodologies.… more
- NVIDIA (Santa Clara, CA)
- …EE background with an in-depth understanding of circuits, simulation, library characterization and static timing analysis? Enjoy working on the cutting edge of ... We are now hiring for a Senior Library Design Engineer ! NVIDIA has...advanced process nodes + Hands-on experience with standard cell timing , power, statistical characterization and modeling. Familiar with advanced… more
- Cisco (San Jose, CA)
- …working with Verilog or System Verilog programming skills + Experience with simulators/synthesis/ static timing constraints and related tools (eg, VCS, DC, ... Senior ASIC Design Engineer Apply (https://jobs.cisco.com/jobs/Login?projectId=1443694)...participate in reviews. + Implement Verilog RTL to meet timing , performance, and power requirements. + Contribute to full… more
- NVIDIA (Santa Clara, CA)
- …distribution, chip assembly and P&R, timing closure. + Craft designs for static timing analysis, power and noise analysis and back-end verification. What we ... We are now looking for a Senior Physical Design Engineer . NVIDIA has...+ Already a validated strong power user of P&R, Timing analysis, Physical Verification and IR Drop Analysis CAD… more
- Microsoft Corporation (Santa Clara, CA)
- …Domain Crossing design techniques. + Proficiency in Verilog, System Verilog, Synthesis and Static Timing Analysis. + Self-motivated and able to work effectively ... Azure Hardware Systems & Infrastructure group is seeking a Senior Silicon Engineer . You will join our...Collaborate with Physical design teams to ensure design meets timing and area requirements. + Work on post-silicon verification… more
- NVIDIA (Santa Clara, CA)
- …algorithms, such as DFE, CTLE, CDR, and offset cancellation + Experience with static timing tools (nanotime, primetime) and formal verification tools + Have ... We are now hiring for a Senior Logic and Digital Circuit Design Engineer...define and build constraints for synthesis and drive for timing closure. In addition to RTL design, you'll need… more
- NVIDIA (Santa Clara, CA)
- …ADC etc. + Hands on experience running Spice simulations, EM/IR analysis, and static timing analysis/closure + Experience with spice simulation for noise ... We are now looking for a motivated Senior Circuit Design Engineer to join...challenging and exciting role in improving the netlist and timing quality of our designs and if you are… more
- The Boeing Company (Mountain View, CA)
- …DSP IP from Boeing's algorithm team and third-party IP as needed + Perform static timing analysis, LEC, CDC, linting, and other necessary checks to ensure ... and/or FPGA Design and Verification Engineers** (Experienced, Lead, or Senior ) to join us as part of our Boeing...Surveillance and Mobility; and Autonomous Systems). As an ASIC/FPGA Engineer on the Boeing Electronic Products team you will… more
- Qualcomm (Santa Clara, CA)
- …as Synposys PrimeTime / Ansys Power Artist + Good understanding of Synthesis and static timing analysis, physical design flow + Good understanding of low power ... optimization of all multimedia use cases. We are looking for a Senior or Staff level Engineer with experience in low power HW design and expertise in Industry… more
- NVIDIA (Santa Clara, CA)
- …2D such as Ansys2D. + Familiarity with power noise budgeting based on core logic static timing requirements or IO power PSIJ requirements. Ways to stand out from ... We are now looking for a Senior Signal & Power Integrity Engineer ! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999… more
- Siemens (Santa Clara, CA)
- …about floor planning, placement, clock tree synthesis, routing, signal & power integrity, and static timing processes. You can teach many of these topics without ... The Job Siemens EDA is looking for an experienced Place & Route user or Applications Engineer to play a critical role in our US-based field team. You will be a key… more
- SpaceX (Sunnyvale, CA)
- …drive execution + Run, debug, and fix signoff closure issues in static timing analysis (STA), noise, logic equivalency, physical verification, electromigration ... hours and weekends as needed COMPENSATION AND BENEFITS: Pay range: Physical Design Engineer / Senior : $170,000.00 - $230,000.00/per year Your actual level and base… more