We interpreted Mountain View, CA as Mountain View, CA. Other options include: Mountain View (Contra Costa County), CA
- NVIDIA (Santa Clara, CA)
- …our life's work, to amplify human inventiveness and intelligence. We are seeking an innovative Senior Timing Methodology Engineer to help drive sign-off ... IR drop etc. + Collaborate with technology leads, VLSI physical design, and timing engineers to define and deploy the most sophisticated strategies of signing off… more
- NVIDIA (Santa Clara, CA)
- …to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Timing Engineer to join our dynamic and growing team. If you want to ... as ECO implementation + Apply knowledge and experience to improve timing convergence flows working with the methodology teams. What we need to see: + BS (or… more
- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. NVIDIA is looking for best-in-class Senior Physical Design Methodology Engineer (s) - PPA Fusion ... improve PPA + Participate in developing flow and tool methodologies for P&R, timing analysis and closure, convergence in IR/Signal-EM, power and noise analysis and… more
- NVIDIA (Santa Clara, CA)
- …human inventiveness and intelligence. What you'll be doing: + Develop and execute timing closure plans for NVIDIA's next generation of high-performance IPs for CPU, ... GPU and SOC designs. + Owning static timing analysis and convergence of high-performance designs. + You...and improve existing flows and methodologies. + Familiarity with methodology and tools, logic synthesis, equivalence checking. + Strong… more
- NVIDIA (Santa Clara, CA)
- We are looking for a Senior CPU Implementation Methodology Engineer to join our VLSI team! If you are looking for a challenging and exciting role and you are ... Deep understanding of logic optimization techniques and relative area, timing , and power trade-offs + Should be a power...the crowd: + Prior CPU experience in physical implementation methodology + Proficiency in Perl, Python, Tcl, Make scripting… more
- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. NVIDIA is looking for best-in-class Senior Physical Design Methodology Engineer (s) to join our ... for chip floorplan, power and clock distribution, chip assembly and P&R, timing analysis and closure, power and noise analysis and back-end verification across… more
- NVIDIA (Santa Clara, CA)
- …are now looking for a Senior Design for Debug (DFD) Architect and Methodology Engineer ! NVIDIA is seeking a DFD Architect to implement hardware and software ... understanding of ASIC design flow including RTL design, verification, logic synthesis, timing analysis and bringup. + Strong interpersonal skills and an excellent… more
- NVIDIA (Santa Clara, CA)
- …floorplanning and chip assembly, power and clock distribution, power and area optimization, timing , IR and EM analysis and closure + Work with internal and external ... partners to drive tool and methodology improvements to deliver best-in-class PPA solutions across all...methods and techniques + Strong background in STA, extraction, timing and RC correlation + Good understanding of design… more
- NVIDIA (Santa Clara, CA)
- …inventiveness and intelligence. We are now looking for a motivated ASIC Physical Design Engineer to join our dynamic and growing team. If you want to challenge ... design space, create optimum floorplan, drive synthesis, physical implementation, and timing closure by understanding arch/logic as well as dataflow and exhibiting… more
- Microsoft Corporation (Santa Clara, CA)
- …Unit (DPU) team within the Azure Hardware Systems & Infrastructure group is seeking a Senior Silicon Engineer . You will join our front-end silicon team and be ... low power, scalable and programmable DPU silicon. As a Senior Silicon Engineer in the Data Processing...+ Review and provide feedback on verification plans and methodology . + Collaborate with Physical design teams to ensure… more
- Cisco (San Jose, CA)
- …, performance, and power requirements. * Contribute to full chip integration and timing methodology /analysis. * Develop and analyze functional coverage. * Help ... define, evolve, and support our design methodology . * Collaborate with the verification team to address...closely with the physical design team to close design timing and place-and-route issues. * Triage, debug, and root… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …for our customers, our communities, and each other-every day. Key Responsibilities The Senior Principal Design Engineer will define the DFT Architecture for the ... other DFT's related logic. Additionally, they will define and develop methodology for DFT insertion, pattern development, manufacturing tests, verifications, etc.… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior Signal Integrity Design Engineer ! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 ... SI model correlations using lab measurements to improve modelling tool/ methodology . + Package substrate and board layout SI design...such as Ansys2D. + Familiarity with a system level timing or loss budget including silicon, package and board… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior Signal & Power Integrity Engineer ! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 ... SI models using data from lab measurements and/or modelling tool/ methodology updates. + Substrate and board layout SI guidelines...such as Ansys2D. + Familiarity with a system level timing or loss budget including silicon, package and board… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior ASIC Design Engineer to join our System ASIC team! NVIDIA has continuously reinvented itself over two decades. Our invention of ... controllers. + You will be responsible for the RTL design, logic synthesis, and timing analysis of several modules. + Integrate modules into the overall SOC design… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior Signal & Power Integrity Engineer ! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 ... SI models using data from lab measurements and/or modelling tool/ methodology updates. + Substrate and board layout SI guidelines...such as Ansys2D. + Familiarity with a system level timing or loss budget including silicon, package and board… more
- Qualcomm (Santa Clara, CA)
- …at connectivity module level, and chip level modes. You will assist with the timing closure of your designs. You will make regular contributions to the overall ... improvement in design methodology to drive productivity and initiatives All Qualcomm employees are expected to actively support diversity on their teams, and in the… more
- NVIDIA (Santa Clara, CA)
- …EE fundamentals, knowledgeable in digital design, computer architecture, power analysis, timing analysis, fault analysis, sampling, statistics, and scripting. + Deep ... + Experience in succeeding in a highly matrix organization. + Driven process/ methodology improvements. NVIDIA is leading the way in groundbreaking developments in… more
- Qualcomm (Santa Clara, CA)
- …full ASIC development process from specification, RTL implementation, verification, synthesis, timing closure, emulation and post silicon bring up. The candidate is ... Experience in SoC low power micro-architecture, low power design and methodology , Power Intent/Implementation, power estimates, power analysis tools and power… more
- Google (Fremont, CA)
- …Analog Digital mixed mode simulation. + Strong background in AMS CAD flow and Methodology . This is a senior individual contributor role requiring a deep ... + Experience in logic design and UVM based simulation. + Experience in creating timing library models for Analog Circuits. + Experience in Memory Array Design. +… more