We interpreted Mountain View, CA as Mountain View, CA. Other options include: Mountain View (Contra Costa County), CA
- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. We are seeking an innovative senior timing signoff and constraint methodology engineer to develop ... this role, you'll develop methodology and flows to validate timing constraints from RTL to netlist via structural, functional and cross-hierarchy … more
- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. We are seeking a highly skilled Timing Methodology Engineer with expertise in asynchronous timing and ... You will play a critical role in defining cross-domain timing constraints , validating IO timing ...equivalent experience). + 6+ years of experience in static timing analysis, methodology , or constraint development. +… more
- NVIDIA (Santa Clara, CA)
- …chip level. + Work with PD, DFX, Clocks, and other teams in coming up with timing closure strategy, creating timing constraints , driving timing and power ... ECO implementation + Apply knowledge and experience to improve timing convergence flows working with the methodology ...in full-chip/sub-chip Static Timing Analysis (STA) and timing convergence, timing constraints generation… more
- NVIDIA (Santa Clara, CA)
- …and convergence of high-performance designs. + You will be responsible for all aspects of timing including setting up timing constraints , timing analysis ... timing closure of high-speed designs. + Strong background and experience in timing constraints generation, clocking, process variations and signal integrity +… more
- Cisco (San Jose, CA)
- …, performance, and power requirements. * Contribute to full chip integration and timing methodology /analysis. * Develop and analyze functional coverage. * Help ... define, evolve, and support our design methodology . * Collaborate with the verification team to address...or System Verilog programming skills * Experience with simulators/synthesis/static timing constraints and related tools (eg, VCS,… more
- Palo Alto Networks (Santa Clara, CA)
- …like setup/hold constraints and delay sources. + Mentor junior and senior staff engineers, providing technical guidance and fostering their growth in ASIC design ... the digital logic that powers our next-generation firewall platforms. As a Senior Principal Engineer, you will take end-to-end ownership of complex modules or… more