- NVIDIA (Santa Clara, CA)
- …team and see how you can make a lasting impact on the world. We seek an RTL Analysis Methodology Engineer to join our Logic Design Implementation team. ... verification methodologies. + Contribute to architecting and developing brand-new RTL analysis flows. + Serve as an...documents and train internal users. + Use data collection, analysis , and reporting tools to provide methodology … more
- NVIDIA (Santa Clara, CA)
- NVIDIA is hiring a SOC/IP Methodology Engineer to help design and architect next generation custom SoC/IP solutions. We are looking for special individuals with ... be a hands-on domain professional, able to traverse from RTL to final design closure (timing and layout) involving...scripting languages + Hands-on experience with physical design and analysis tools from EDA vendors such as Cadence, Synopsys,… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior Design for Debug (DFD) Architect and Methodology Engineer ! NVIDIA is seeking a DFD Architect to implement hardware and software ... tools. + Great understanding of ASIC design flow including RTL design, verification, logic synthesis, timing analysis ...including RTL design, verification, logic synthesis, timing analysis and bringup. + Strong interpersonal skills and an… more
- Meta (Sunnyvale, CA)
- …with experience in front-end implementation from RTL to netlist, including RTL Lint, CDC analysis , timing constraints, synthesis to build efficient System ... Perform RTL Lint and work with the Designers to create waivers. 5. Perform RTL DFT Analysis and improve the DFT coverage for Stuck-at faults. 6. Perform Flat… more
- NVIDIA (Santa Clara, CA)
- …Chip Leads, and Customers on SOC IP design, development, timing closure, power analysis , methodology alignment, and program execution to ensure pre-silicon and ... NVIDIA is hiring a Senior Design Engineer to design, analyze, and evolve next generation...of external and internal IPs. + Contribute to cross-team RTL methodologies to achieve efficient design reuse. + Evaluate… more
- Qualcomm (Santa Clara, CA)
- …drive CPU timing closure for Oryon CPU Cores. As a CPU Physical Design Timing Engineer , you will work with microarchitecture and RTL design team to develop ... STA native tools and also useful in enabling CPU timing infrastructure and methodology impacting multiple CPU projects in Qualcomm. You will have the opportunity to… more
- Meta (Sunnyvale, CA)
- …in HLS 17. Experience with Synthesis, Timing Closure and Formal Verification Methodology 18. Experience with Power Analysis and Optimization 19. Experience ... and IP for data center applications. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Architecture exploration 2. Micro-architecture development 3.… more
- Siemens Digital Industries Software (Fremont, CA)
- …+ Working knowledge of IC EDA tools and design methods including: o ASIC design methodology from RTL Synthesis to Physical Implementation phases o RTL ... planning, physical design/verification, muti-die based electrical, thermal, mechanical stress analysis and manufacturing test of advanced 2.5 and 3D… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …(TCL and Perl) Proficiency with synthesis, logic equivalence, DFT and backend related methodology and tools Strong background in Constraint analysis and debug, ... span across various aspects for the ASIC frontend flow, which includes RTL integration, maintain the timing constraint, Synthesis, Place and Route, Static timing… more
- BAE Systems (San Jose, CA)
- …strong proficiency in both + ASIC design- performing architecture design, RTL coding/simulation, timing closure at layout phase + Verification- executing testbench ... creation, functional coverage, test failures analysis , regression Detail requirements + Front..., regression Detail requirements + Front End Design and RTL coding of high-speed digital circuits on ASIC/FPGAs from… more
- NVIDIA (Santa Clara, CA)
- …reduce power consumption of NVIDIA GPUs. As a member of the Power Modeling, Methodology and Analysis Team, you will collaborate with Architects, ASIC Design ... We are now looking for an Architecture Energy Modeling Engineer ! At NVIDIA, we pride ourselves in having energy-efficient products. We believe that continuing to… more
- NVIDIA (Santa Clara, CA)
- …verification methodology + Good understanding of ASIC design flow including RTL design, verification, logic synthesis and timing analysis + Excellent ... for System-level modules (Fuse, Strap, Floorsweep, In-silicon measurement, Reset, Sysctrl) + RTL design, synthesis, timing + Silicon bring-up + SOC level integration… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a motivated Senior ASIC Engineer , Timing to join our dynamic and growing team. If you are looking for a challenging and exciting role in ... asynchronous checking including clock domain crossing checks and MTBF analysis , logic synthesis, netlist quality checks, etc. + Help...teams. + Work on project execution as well as methodology improvements. What we need to see: + BS… more
- Amazon (Sunnyvale, CA)
- …is powering the latest generation of Echo devices is looking for a Sr. SOC Design Engineer -STA to continue to innovate on behalf of our customers. We are a part of ... Roles & Responsibilities: - Includes definition and development of signoff methodology and corresponding implementation solution - Flow for STA, Crosstalk Delay… more
- Siemens Digital Industries Software (San Jose, CA)
- …* Drive products into customer projects through to adoption by creating methodology and flows; this may include infrastructure and integration into a customer's ... 3 to 8 years of experience as an Applications Engineer , ASIC Design Engineer or related field... or related field * Digital design experience and RTL coding with Verilog or VHDL or both *… more
- Siemens Digital Industries Software (Fremont, CA)
- …Functional verification and modeling of digital/mixed-signal ASICs and SoCs, Failure analysis and resolution, Coverage analysis , RTL /Gate-simulations, ... expect competent leadership from our managers and executives. This Applications Engineer (AE) position delivers technical expertise for Functional Verification of… more
- Amazon (Sunnyvale, CA)
- …is powering the latest generation of Echo devices is looking for a Sr. Physical Design Engineer to continue to innovate on behalf of our customers. We are a part of ... for driving efficiency and quality improvements to the overall FC methodology - including floorplan optimization for better utilization/QoR/runtime and timing and… more
- NVIDIA (Santa Clara, CA)
- …and intelligence. Be part of a diverse team creating NVIDIA's chip design methodology ! We're responsible for the Front-End Design Implementation methodology for ... to evaluate the industry's most powerful design implementation and analysis tools + Provide support for ASIC tools and...Learning + Experience in other ASIC methodologies such as RTL Lint, CDC, DFT or STA. + Experience with… more