- Cisco (San Jose, CA)
- …You'll Work With: You will be in the Silicon One development organization as a senior DFT verification lead in San Jose, CA. You will work with Front-end RTL ... physical design teams to understand chip architecture and drive high-quality DFT verification . What You'll Do: * Responsible for thorough test planning and… more
- Cisco (San Jose, CA)
- …industry. Your Impact: You will be in the Silicon One development organization as an ASIC Implementation Technical Lead in San Jose, CA with a primary focus on ... developing custom DFT logic & IP integration; familiarity with functional verification Preferred Qualification: * DFT CAD development - Test Architecture,… more
- Meta (Sunnyvale, CA)
- …on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Implementation Engineer - Static Verification Responsibilities: 1. Perform Flat ... **Summary:** Meta is hiring ASIC Frontend Implementation Engineers within our Infrastructure organization....with the Designers to create waivers. 4. Perform RTL DFT Analysis and improve the DFT coverage… more
- Cisco (San Jose, CA)
- …service provider networks. Cisco's silicon team provides a unique experience for ASIC engineers by combining the resources offered by a large multi-geography silicon ... breadth of growth opportunities that working in a smaller ASIC team can provide. You will work with exceptional...oversees fullchip SDCs and works with physical design and DFT teams to close fullchip timing in multiple timing… more
- Cisco (San Jose, CA)
- …service provider networks. Cisco's silicon team provides a unique experience for ASIC engineers by combining the resources offered by a large multi-geography silicon ... breadth of growth opportunities that working in a smaller ASIC team can provide. You will work with exceptional...fullchip SDCs and work with the Physical Design and DFT teams to close fullchip timing in multiple timing… more
- Cisco (San Jose, CA)
- …* Help define, evolve, and support our design methodology. * Collaborate with the verification , PD, DFT , Package and SW teams to develop next generation ASICs. ... will engage in dynamic collaboration with Senior micro-architects, designers, verification engineers and interact with cross-functional software and product teams,… more
- Meta (Sunnyvale, CA)
- **Summary:** Meta is hiring ASIC Implementation Engineers within our Infrastructure organization. We are looking for individuals with experience in front-end ... Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Implementation Engineer - Synthesis Responsibilities: 1. Run Logic/Physical Synthesis using… more
- Meta (Sunnyvale, CA)
- **Summary:** Meta is hiring ASIC Implementation Engineers within our Infrastructure organization. We are looking for individuals with experience in front-end ... Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Implementation Engineer - Synthesis Responsibilities: 1. Run Logic/Physical Synthesis using… more
- Broadcom (San Jose, CA)
- …with GLS with & without parasitic annotated simulations + Prior experience in verification of the DFT design, architecture, and microarchitecture + Experience in ... this highly visible role you will be working on ASIC for data center connectivity applications.Qualifications include: + BSc...developing verification environments for various DFT patterns like,… more
- Cisco (San Jose, CA)
- …partner organizations such as the Corporate Hardware Group to bring complex Cisco ASIC & Switch products to market. You will also engage closely with engineering ... bring-up and diagnostics teams, test & verification teams, and Product Quality teams to identify and...the NPI or Production processes. Your Impact As a Technical Leader in Silicon Reliability, you will play a… more
- Google (Sunnyvale, CA)
- … verification , and signoff. Preferred qualifications: + Experience in ASIC physical design, physical design flows, and methodologies including synthesis, place ... and route, Static Timing Analysis (STA), formal verification , Change Data Capture (CDC), and power analysis. +...Design you will collaborate with the architecture, logic design DFT , physical design, and circuits/technology teams to overcome the… more
- Google (Sunnyvale, CA)
- …degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field, or equivalent practical experience. + 7 years of experience ... static timing (ie, full chip timing signoff ownership, constraint authoring and verification , full chip static timing analysis and timing ECO creation, timing… more