• ASIC Design Efficiency

    NVIDIA (Santa Clara, CA)
    We are now looking for an ASIC Design Efficiency Engineer . NVIDIA is seeking extraordinary methodology engineers to design hardware accelerators and ... to extend the state of the art performance and efficiency . + Understand the design and implementation,...art performance and efficiency . + Understand the design and implementation, develop methodology and infrastructure to drive… more
    NVIDIA (06/27/25)
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  • Senior ASIC Design Engineer

    NVIDIA (Santa Clara, CA)
    We are now looking for a Senior ASIC Design Engineer to join our System ASIC team! NVIDIA has continuously reinvented itself over two decades. Our ... choice to join us today. NVIDIA is seeking best-in-class ASIC Design Engineers to design ...expertise to identify and implement improvements in the current design flow and methodologies to improve efficiency more
    NVIDIA (06/19/25)
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  • ASIC Rtl Design Engineer

    Google (Sunnyvale, CA)
    …hardware experiences, delivering unparalleled performance, efficiency , and integration. As a Design Engineer , you will play an important role in designing ... + 5 years of experience in Application-specific integrated circuit ( ASIC ) design . + Experience working on interconnects...use Google services around the world. We prioritize security, efficiency , and reliability across everything we do - from… more
    Google (07/01/25)
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  • ASIC Design Engineer - New…

    NVIDIA (Santa Clara, CA)
    …has never been a more exciting time to join our team! NVIDIA is seeking outstanding ASIC Design Engineers to design and implement the world's leading GPU and ... doing: + Be an integral part of the System ASIC Design team to help develop and...expertise to identify and implement improvements in the current design flow and methodologies to improve efficiency more
    NVIDIA (06/28/25)
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  • ASIC Power Efficiency

    Google (Sunnyvale, CA)
    …a related field, or equivalent practical experience. + 3 years of experience in ASIC design or equivalent practical experience. + Experience in chip power ... and benchmarks for measuring chip power consumption. + Develop design improvements to increase power efficiency . +...+ Develop design improvements to increase power efficiency . + Collaborate with cross-functional teams in defining power… more
    Google (06/17/25)
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  • Senior ASIC Design Engineer

    NVIDIA (Santa Clara, CA)
    NVIDIA is seeking an outstanding Senior ASIC Design Engineer to design and implement the world's leading SoC's and GPU's. This position offers the ... Systems design . + A deep understanding of ASIC design flow including RTL design...virtual channels. + Interest or have prior experience in efficiency enhancement, such as, flow development and code generator.… more
    NVIDIA (05/02/25)
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  • Senior Reset and Boot ASIC Engineer

    NVIDIA (Santa Clara, CA)
    NVIDIA is looking for a Senior Reset and Boot ASIC Engineer to join our System ASIC team! NVIDIA has continuously reinvented itself over two decades. Our ... choice to join us today. NVIDIA is seeking best-in-class ASIC Design Engineers to design ...expertise to identify and implement improvements in the current design flow and methodologies to improve efficiency more
    NVIDIA (06/18/25)
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  • ASIC Methodology/CAD Engineer

    Amazon (Sunnyvale, CA)
    …robot. What will you help us create? As an ASIC Methodology / CAD engineer you will create and maintain automated design flows that improve the efficiency ... and design quality of the finished ASIC products. Key job responsibilities - Develop automated flows...responsibilities - Develop automated flows for improving the SoC design process - Build robust, scalable tools that help… more
    Amazon (06/11/25)
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  • ASIC Engineer , IP Design

    Google (Mountain View, CA)
    …or equivalent practical experience. + 8 years of experience with RTL design using Verilog/System Verilog and microarchitecture. + Experience with a scripting ... like Python or Perl. + Experience with ARM-based SoCs, interconnects and ASIC methodology. Preferred qualifications: + Master's degree or PhD in Electrical… more
    Google (06/14/25)
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  • Senior ASIC Power Engineer

    NVIDIA (Santa Clara, CA)
    We are now looking for a Senior ASIC Power Engineer ! NVIDIA is seeking extraordinary power engineers to design hardware accelerators and processors on our ... efficiency + You are expected to understand the design and implementation, develop power metrics and drive power...want to hear from you. Come, join our GPU ASIC team and help build the real-time, cost-effective computing… more
    NVIDIA (04/23/25)
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  • Senior ASIC Front End Infrastructure…

    NVIDIA (Santa Clara, CA)
    NVIDIA is seeking elite ASIC RTL/Verification ASIC engineers to develop the core Verification and RTL infrastructure of the world's leading GPUs. This position ... team of dedicated Infrastructure engineers continuously upgrades the NVIDIA Hardware design environment. We focus relentlessly on Infrastructure improvement so that… more
    NVIDIA (04/30/25)
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  • ASIC SoC System Level Test Engineer

    Google (Sunnyvale, CA)
    …with System Level Test (SLT) or product engineering. + Experience with ASIC or SoC prototype bring-up, debug, functional verification or functional manufacturing ... test automation, and test deployment actively contributing to technical design and problem-solving. + Experience implementing secure manufacturing solutions… more
    Google (07/09/25)
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  • Senior Software Engineer , ASIC

    NVIDIA (Santa Clara, CA)
    …years of EDA tool development in the verification field + Hands on experience with ASIC design and verification + Good with C++ and other programming languages ... engineers on project verification support + Develop new methodologies to improve verification efficiency and capacity + Co-develop EDA tools with our vendors to best… more
    NVIDIA (05/02/25)
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  • Static Timing Analysis Engineer , FullChip/…

    Google (Mountain View, CA)
    …with high complexity silicon in state-of-the-art technology process nodes. + Experience with ASIC design flows and methodology of static timing analysis. + ... Experience in extraction of design parameters, QoR metrics, and analyzing data trends. +...the next generation of hardware experiences, delivering unparalleled performance, efficiency , and integration. The US base salary range for… more
    Google (06/21/25)
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  • Package Design Engineer

    Meta (Menlo Park, CA)
    …create as part of a world-class engineering team. **Required Skills:** Package Design Engineer Responsibilities: 1. Drive chip-package-system co- design by ... **Summary:** Meta is looking for an experienced ASIC Packaging Engineer , Signal Integrity, and...silicon, architecture and system teams and externally engaged partners, ASIC design partners, foundry and OSAT and… more
    Meta (06/28/25)
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  • SoC RTL Security Design Engineer

    Google (Sunnyvale, CA)
    …experiences, delivering unparalleled performance, efficiency , and integration. As a SoC Design Engineer , you will join a team working on SoC-level RTL ... on computer architecture. + 10 years of experience in ASIC design with 3 years of experience...use Google services around the world. We prioritize security, efficiency , and reliability across everything we do - from… more
    Google (06/05/25)
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  • Senior Hardware Engineer | Hardware…

    Cisco (Milpitas, CA)
    Senior Hardware Engineer | Hardware Design | Routers Apply (https://jobs.cisco.com/jobs/Login?projectId=1446399) + Location:Milpitas, California, US + Alternate ... hardware for the 8000 series routers to deliver the best quality, best power efficiency using cutting edge series technology at the highest bit rates possible. Your… more
    Cisco (07/10/25)
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  • Senior RTL Design Engineer , Silicon

    Google (Mountain View, CA)
    …degree in Electrical Engineering, Computer Engineering or Computer Science. + Experience with ASIC design methodologies for clock domain checks, reset checks and ... experience. + 8 years of experience with digital logic design principles, RTL design concepts, and languages,...Knowledge of FPGA and emulation platforms. + Knowledge of ASIC Verification or DFT. Be part of a team… more
    Google (06/27/25)
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  • Senior Signal Integrity Engineer (Hardware)

    Palo Alto Networks (Santa Clara, CA)
    …to validate critical interfaces. Within the Hardware team, you collaborate closely with Board Design , ASIC Design , PCB Layout, and Validation Test. You will ... Component Engineers. **Your Impact** + Collaborate with a cross-functional team including: ASIC , Board design , PCB layout, Operations supply base management,… more
    Palo Alto Networks (06/27/25)
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  • Principal Engineer - Silicon One Software

    Cisco (San Jose, CA)
    …are received. **Meet the Team** Cisco Silicon One is the center of Cisco's ASIC design and is driving the development of next-generation network devices for ... Principal Engineer - Silicon One Software Apply (https://jobs.cisco.com/jobs/Login?projectId=1443934) +...design teams to define the next generation of ASIC products being developed. You will work multi-functionally with… more
    Cisco (07/05/25)
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