- NVIDIA (Santa Clara, CA)
- We are now looking for a ASIC Floorplan Design Engineer - NCG. NVIDIA is seeking a talented ASIC Floorplan Engineer to design and ... development. + Drive the area review process and collaborate with the ASIC design team to identify area, interconnect and floorplan improvement opportunities… more
- Palo Alto Networks (Santa Clara, CA)
- …is to create an environment where we all win with precision. **Your Career** As a Design engineer on the ASIC team, you will create complex digital logic ... testability in close collaboration with ASIC physical design engineers + Perform synthesis + Optimize floorplan...military experience required + Minimum 8 years experience in ASIC design + Demonstrated success in taking… more
- NVIDIA (Santa Clara, CA)
- …work, to amplify human inventiveness and intelligence. We are now looking for a motivated ASIC Physical Design Engineer to join our dynamic and growing team. ... PPA for high-performance designs, eg Nvidia's CPUs and GPUs. + Explore design space, create optimum floorplan , drive synthesis, physical implementation, and… more
- Meta (Sunnyvale, CA)
- …(Power, Performance, and area) of the design . **Required Skills:** Silicon Physical Design Engineer Responsibilities: 1. Develop and own physical design ... ML Hardware design including physical-aware logic synthesis, floorplan , place and route, static timing analysis, IR Drop,...equivalent practical experience. 7. 10+ years of experience in ASIC Physical Design 8. Understanding of RTL2GDSII… more
- Cisco (San Jose, CA)
- …for SOC physical design teams. * Experience working with Package and floorplan teams to define padring and bump-map design . WeAreCisco #WeAreCisco where ... As a Technical Leader, you will be responsible for overseeing the design and verification of application-specific integrated circuits (ASICs), ensuring they meet… more
- Google (Sunnyvale, CA)
- …a related field, or equivalent practical experience. + 3 years of experience in ASIC physical design flows with emphasis on physical verification convergence and ... for full chip assembly and tapeout signoff. + Work with floorplan and physical design engineers to drive physical verification convergence. + Perform technical… more