- Cisco (San Jose, CA)
- …most complex ASICs being developed in the industry. Your Impact You'll be joining our Physical Design team at Cisco Silicon One group, which is responsible for ... or equivalent similar experience. * 10+ years of experience in Physical Design . * Experience working on Fullchip activities. * Experience with RTL2GDSII… more
- Cisco (San Jose, CA)
- … ASIC team can provide. You will work with exceptional talent with vast ASIC design and development expertise. With Cisco being a systems company, you will ... networks. Cisco's silicon team provides a unique experience for ASIC engineers by combining the resources offered by a...refining design and timing constraints for seamless physical design closure. As part of this… more
- Meta (Sunnyvale, CA)
- **Summary:** Meta is hiring ASIC Physical Design Engineers within our Infrastructure organization. We are looking for individuals with experience in backend ... efficient System on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Engineer, Physical Design Responsibilities: 1. Develop and own … more
- Palo Alto Networks (Santa Clara, CA)
- …meet aggressive goals for area, timing, power, and testability in close collaboration with ASIC physical design engineers + Perform synthesis + Optimize ... military experience required + Minimum 8 years experience in ASIC design + Demonstrated success in taking...+ Debugging simulation, emulation, and silicon validation + Analyzing physical design reports and fixing timing and… more
- Meta (Menlo Park, CA)
- **Summary:** Meta is seeking a Technical Program Manager with ASIC design and development experience. This Technical Program Manager (TPM) will lead ... technical details to big picture 12. Experience in managing ASIC design flow (architecture, micro-architecture, RTL, Synthesis, functional verification, … more
- Cisco (San Jose, CA)
- … ASIC team can provide. You will work with exceptional talent with vast ASIC design and development expertise. With Cisco being a systems company, you will ... networks. Cisco's silicon team provides a unique experience for ASIC engineers by combining the resources offered by a...refining design and timing constraints for seamless physical design closure. As part of this… more
- SanDisk (Milpitas, CA)
- …seamless integration of ASIC designs into larger systems + Conduct thorough design reviews and provide technical leadership to junior engineers + Analyze and ... development + Contribute to the development of best practices and methodologies for ASIC design within the organization + Optimize designs for power efficiency,… more
- Meta (Sunnyvale, CA)
- …( ASIC Development tools, Compute/Storage/Licensing management,etc.) and/or CAD Methodology ( Physical Design , Timing Methodology, Physical Verification, ... and Enterprise Engineering teams on adapting FB infrastructure to ASIC design solutions, including but not limited...meet the needs of internal customers. 6. Partner with technical program management and supply chain team members to… more
- Cisco (San Jose, CA)
- …Do Be part of the development organization as an ASIC Engineering Technical Leader with primary focus on RTL Design . * Create micro-architecture ... bugs and close code coverage. * Work closely with physical design team to close design...work with SDK and Software teams as part of ASIC development to create a seamless handshake between hardware… more
- Cisco (San Jose, CA)
- …focus on Design -for-Test. You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive DFT requirements ... be in the Silicon One development organization as an ASIC Implementation Technical Lead in San Jose,...participate in the creation of Innovative Hardware DFT & physical design aspects for new silicon device… more
- Meta (Sunnyvale, CA)
- …Engineers in supporting them with the handoff tasks. 11. Interact with Physical Design Engineers and provide them with timing/congestion feedback. **Minimum ... in SOC Design Integration and Front-End Implementation. 20. Knowledge of Physical Design flow such as Floorplanning, CTS, Routing 21. Good Understanding… more
- Meta (Sunnyvale, CA)
- …Emulation Engineers in supporting them with the handoff tasks. Interact with Physical Design Engineers and provide them with timing/congestion feedback. ... in SOC Design Integration and Front-End Implementation. 18. Knowledge of Physical Design flow such as Floorplanning, CTS, Routing 19. Good Understanding… more
- Meta (Sunnyvale, CA)
- …Emulation Engineers in supporting them with the handoff tasks. Interact with Physical Design Engineers and provide them with timing/congestion feedback. ... 12. Knowledge of SOC Integration (Clocking, Reset, PLL, etc) 13. Knowledge of front-end ASIC flows 14. Experience with RTL design using SystemVerilog or other… more
- Meta (Sunnyvale, CA)
- …Emulation Engineers in supporting them with the handoff tasks. 8. Interact with Physical Design Engineers and provide them with timing feedback. **Minimum ... **Summary:** Meta is hiring ASIC Frontend Implementation Engineers within our Infrastructure organization....DFT Modes. 4. Perform STA for full chip and Physical partition blocks using PrimeTime 5. Run Logic/ Physical… more
- Amazon (Sunnyvale, CA)
- …Verification LEC DRC LVS etc. - Be single point contact for bugs and issues for physical design team - Build flow in TCL, Python to ensure quality and faster ... semiconductor projects. This is an opportunity to shape the technical direction of critical IC design workflows...infrastructure - 7+ years of silicon EDA and/or digital ASIC design experience Preferred Qualifications - Master's… more
- Cisco (San Jose, CA)
- …lead in San Jose, CA. You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive high-quality DFT ... hardware platforms for Cisco's core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers of various… more
- Meta (Sunnyvale, CA)
- … technical field, or equivalent practical experience. 7. 10+ years of experience in ASIC Physical Design 8. Understanding of RTL2GDSII flow and design ... Machine Learning (ML) front-end and back-end hardware designers to drive the Physical design implementation of ML compute blocks in advanced technology nodes and… more
- Cisco (San Jose, CA)
- …as per need for verification robustness. * Guide and mentor a team of physical design engineers on project-level backend implementation and partner closely with ... and automate workflows. * Experience working with one or more of the following physical design tools, such as Cadence, Innovus, Synopsys IC Compiler, or Fusion… more
- Meta (Sunnyvale, CA)
- …from transistors, through architecture, firmware, and algorithms.We are growing our Machine Learning ASIC Design and uArchitecture team within RL and are seeking ... 5. Work cross-functionally with adjacent chip-level teams such as Verification, Physical Design , and Design -for-Test **Minimum Qualifications:** Minimum… more
- Google (Sunnyvale, CA)
- …or a related field, or equivalent practical experience. + 10 years of experience in ASIC physical design and methodologies in advanced process nodes. + ... stack, including timing, PDV, EMIR, package concerns, and power. + Experience with custom physical design , which may include custom datapath design , standard… more