• ASIC Power Efficiency

    Google (Sunnyvale, CA)
    …measuring chip power consumption. + Develop design improvements to increase power efficiency . + Collaborate with cross-functional teams in defining power ... using EDA tools such as PTPX, PowerArtist, or PrimePower. + Experience driving power - efficiency improvement in chip designs. + Experience with pre-silicon vs… more
    Google (06/17/25)
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  • Senior ASIC Power Engineer

    NVIDIA (Santa Clara, CA)
    We are now looking for a Senior ASIC Power Engineer ! NVIDIA is seeking extraordinary power engineers to design hardware accelerators and processors on ... to extend the state of the art performance and efficiency + You are expected to understand the design...are expected to understand the design and implementation, develop power metrics and drive power reductions +… more
    NVIDIA (04/23/25)
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  • ASIC Design Efficiency

    NVIDIA (Santa Clara, CA)
    We are now looking for an ASIC Design Efficiency Engineer . NVIDIA is seeking extraordinary methodology engineers to design hardware accelerators and ... and system designs to extend the state of the art performance and efficiency . + Understand the design and implementation, develop methodology and infrastructure to… more
    NVIDIA (06/27/25)
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  • ASIC Rtl Design Engineer

    Google (Sunnyvale, CA)
    …will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency , and integration. As a Design Engineer , you will play ... + Experience with industry-standard EDA tools for simulation, synthesis, and power analysis. Preferred qualifications: + Master's degree or PhD in Electrical… more
    Google (07/01/25)
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  • Senior ASIC Design Engineer

    NVIDIA (Santa Clara, CA)
    NVIDIA is seeking an outstanding Senior ASIC Design Engineer to design and implement the world's leading SoC's and GPU's. This position offers the opportunity to ... Computer Architecture and Digital Systems design. + A deep understanding of ASIC design flow including RTL design, verification, logic synthesis, timing analysis,… more
    NVIDIA (05/02/25)
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  • ASIC SoC System Level Test Engineer

    Google (Sunnyvale, CA)
    …with System Level Test (SLT) or product engineering. + Experience with ASIC or SoC prototype bring-up, debug, functional verification or functional manufacturing ... team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to...use Google services around the world. We prioritize security, efficiency , and reliability across everything we do - from… more
    Google (07/09/25)
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  • ASIC Engineer , IP Design, Silicon

    Google (Mountain View, CA)
    …like Python or Perl. + Experience with ARM-based SoCs, interconnects and ASIC methodology. Preferred qualifications: + Master's degree or PhD in Electrical ... industry experience with IP design. + Experience with methodologies for low power estimation, timing closure, synthesis. + Experience with methodologies for RTL… more
    Google (06/14/25)
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  • Static Timing Analysis Engineer , FullChip/…

    Google (Mountain View, CA)
    …high complexity silicon in state-of-the-art technology process nodes. + Experience with ASIC design flows and methodology of static timing analysis. + Experience in ... of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the… more
    Google (06/21/25)
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  • Senior Power Architecture and Optimization…

    NVIDIA (Santa Clara, CA)
    power data, and driving ASIC teams to improve their units' power efficiency ; and is responsible for researching, developing, and deploying methodologies ... We are now looking for a Senior Power Architecture and Optimization Engineer ! NVIDIA... power analysis tools, to help improve product power efficiency . + Develop and share best… more
    NVIDIA (06/17/25)
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  • Senior Emulation Power Engineer

    NVIDIA (Santa Clara, CA)
    power data and driving ASIC teams to improve their units' power efficiency ; and is responsible for researching, developing, and deploying methodologies to ... We are looking for a Senior Emulation Power Engineer ! NVIDIA prides in having...concepts of energy consumption, estimation, data movement and low power design. + Familiarity with Verilog and ASIC more
    NVIDIA (05/29/25)
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  • Package Design Engineer

    Meta (Menlo Park, CA)
    **Summary:** Meta is looking for an experienced ASIC Packaging Engineer , Signal Integrity, and Power Integrity focus for its ASIC packaging team to ... to develop packaging solutions that are optimal for our ASIC roadmap. We are building a competency in Packaging...such as 2.5D/3D and heterogeneous integration to improve bandwidth, power efficiency and package form factor for… more
    Meta (06/28/25)
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  • Server Chipset Power Engineer

    Qualcomm (Santa Clara, CA)
    …are highly optimized for the needs of the server product. **Position: Server Chipset Power Engineer ** We are seeking a highly experienced Server Chipset Power ... innovative solutions that push the limits of performance, energy efficiency , and scalability. Our focus is on developing server-class... and silicon/system limits + Strong fundamentals in digital ASIC design and power of CMOS circuits… more
    Qualcomm (05/08/25)
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  • Senior System Performance and Power

    NVIDIA (Santa Clara, CA)
    …a trailblazer at the forefront of graphics and artificial intelligence performance, efficiency , and innovation. From our roots as a groundbreaking graphics company, ... industries. NVIDIA Silicon Solutions Group is seeking a versatile engineer to be part of the HW ArchDev team....Build roadmaps of system level features to address low power , low noise, perf/watt efficient product needs by doing… more
    NVIDIA (06/20/25)
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  • Principal Engineer - Silicon One Software

    Cisco (San Jose, CA)
    …for universal adaptability, delivering high speed without sacrificing programmability, buffering, power efficiency , scale, or feature flexibility. The Cisco ... Principal Engineer - Silicon One Software Apply (https://jobs.cisco.com/jobs/Login?projectId=1443934) +...Team** Cisco Silicon One is the center of Cisco's ASIC design and is driving the development of next-generation… more
    Cisco (07/05/25)
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  • Senior Signal Integrity Engineer (Hardware)

    Palo Alto Networks (Santa Clara, CA)
    …integrity analysis of ASIC and multi-chip-module designs + Model and analyze power delivery networks for ASIC /package/module and PCB + Create SI test plan ... Experience** + Strong background in hands-on design and validation of high-speed PCB and ASIC package development + Power integrity design and analysis and well… more
    Palo Alto Networks (06/27/25)
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  • Principal DSP Engineer - Coherent Optical…

    Cisco (San Jose, CA)
    …from the DSP and ASIC teams is key to optimizing performance and power efficiency . You'll contribute to system design, develop architectures, and support ... Principal DSP Engineer - Coherent Optical Transmission Systems - Acacia Apply...ASIC design and verification. Work closely with colleagues across various… more
    Cisco (07/05/25)
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  • SoC RTL Security Design Engineer

    Google (Sunnyvale, CA)
    …will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency , and integration. As a SoC Design Engineer , you will ... Experience with industry-standard EDA tools for simulation, synthesis and power analysis. Preferred qualifications: + Master's degree or PhD...on computer architecture. + 10 years of experience in ASIC design with 3 years of experience working on… more
    Google (06/05/25)
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  • Senior Hardware Engineer | Hardware Design…

    Cisco (Milpitas, CA)
    …the hardware for the 8000 series routers to deliver the best quality, best power efficiency using cutting edge series technology at the highest bit rates ... Senior Hardware Engineer | Hardware Design | Routers Apply (https://jobs.cisco.com/jobs/Login?projectId=1446399)...Cadence/Allegro to capture schematics_ + _Bring up hardware with ASIC teams_ + _Debug issues the lab using analyzers,… more
    Cisco (07/10/25)
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  • Software Engineer , Silicon One Engineering

    Cisco (San Jose, CA)
    …for universal adaptability, delivering high speed without sacrificing programmability, buffering, power efficiency , scale, or feature flexibility. The Cisco ... Software Engineer , Silicon One Engineering Apply (https://jobs.cisco.com/jobs/Login?projectId=1443499) + Location:San...Team** Cisco Silicon One is the center of Cisco's ASIC design and is driving the development of next-generation… more
    Cisco (07/10/25)
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  • Senior Technical Leader Software Engineer

    Cisco (San Jose, CA)
    …for universal adaptability, delivering high speed without sacrificing programmability, buffering, power efficiency , scale, or feature flexibility. The Cisco ... Senior Technical Leader Software Engineer , Cisco Silicon One (L2/L3) Apply (https://jobs.cisco.com/jobs/Login?projectId=1441663) +...Team** Cisco Silicon One is the center of Cisco's ASIC design and is driving the development of next-generation… more
    Cisco (07/01/25)
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