- Amazon (Sunnyvale, CA)
- …Edge that is powering the latest generation of Echo devices is looking for a Senior SoC Design - STA Engineer to continue to innovate on behalf of our ... STA and Signoff for a complex, multi-clock, multi-voltage SoC . * Streamlining the timing signoff criterions, timing analysis...& Route and other local/remote teams to address the design challenges in the context of timing sign-off. *… more
- Meta (Sunnyvale, CA)
- … documentation including IP/ SoC Micro Architecture document (collaborator/owner), IP/ SoC Design plan (collaborator) and SoC /chip bringup/validation ... with Digital Verification (DV) 3. Support back end physical design (PD) through STA and SDCs 4....SPI, UART, etc 20. Familiar with IP, sub-system and SoC Design Verification to execute Design… more
- Google (Mountain View, CA)
- …in silicon timing closure and chip integration. + Experience with STA signoff constraint authoring for full-chip level, tapeout signoff requirements, checklists, ... complexity silicon in state-of-the-art technology process nodes. + Experience with ASIC design flows and methodology of static timing analysis. + Experience in… more
- Meta (Sunnyvale, CA)
- … from a timing/sign-off perspective 17. Experience with Register-Transfer Level (RTL) design using SystemVerilog or other Hardware Description Language (HDL) 18. ... Infrastructure organization, where you'll play a critical role in developing design integrity and signoff methodologies for large complex disaggregated ASICs. Your… more
- NVIDIA (Santa Clara, CA)
- … hardware engineering position. + Previous engineering experience in CPU/GPU/ SOC NPI bringup, with focus on driving methodologies and testplans. Familiarity ... a plus, related to timing, speed, reliability and power. + Familiarity with STA timing closure, circuit design , noise characterization, product binning methods… more