- Cadence Design Systems, Inc. (San Jose, CA)
- …on SDC constraints, advanced OCV/SOCV concepts, derates, PBA timing, Distributed and Concurrent STA flows. . Work efficiently with R&D and customer to enable various ... timing analysis & ECO flows including newer advanced technologies. . Performing timing correlation, tool feature benchmarking, constraints validation, spice analysis on various tech nodes and customer designs. . Work on In-design timing ECO optimizations… more
- Qualcomm (Santa Clara, CA)
- …for skilled engineers to focus on timing constraints development, power analysis, STA , and timing closure for premium-tier chips. This is an excellent opportunity ... in Tcl, Perl, or Python are also desirable. **Job Description: Principal Duties and Responsibilities** + Develop constraints for physical power-aware synthesis,… more
- Qualcomm (Santa Clara, CA)
- …to help create a smarter, connected future for all. As a Qualcomm CPU Engineer , you will lead innovative Central Processing Unit (CPU) design efforts that have a ... in IC design** . + **Experience in leading block level or chip level Physical Design, STA and PDN activities** . + Work independently in the areas of RTL to GDSII… more
- Qualcomm (Santa Clara, CA)
- …push the envelope on performance, energy efficiency and scalability. As CPU EM/IR CAD engineer , you will build and support the world's best analysis tools and flows. ... user of Ansys Redhawk SC power integrity analysis toll and have exposure to PnR/ STA and extraction industry standard tools and flow + Support and enhance static IR,… more