- Syntiant (Redwood City, CA)
- …the high-growth AI software and semiconductor solutions space, is looking for an experienced and talented Senior Staff ASIC Design Engineer to take on a ... a leading role in enhancing the Hardware Engineering in a growing organization. As Digital ASIC Design Engineer , you will be a key player in the ASIC R&D… more
- Amazon (Sunnyvale, CA)
- …low-latency, high-speed broadband connectivity. Come work at Amazon! The Role: As Senior CAD Engineer you will be responsible for installing and maintaining EDA ... tools and flows for project Kuiper's digital design teams. This is an opportunity to define the...work safely and cooperatively with other employees, supervisors, and staff ; adhere to standards of excellence despite stressful conditions;… more
- Qualcomm (Santa Clara, CA)
- …Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design , verification, validation, integration, or related work experience. OR ... Science, Engineering, or related field and 5+ years of ASIC design , verification, validation, integration, or related...influence over key organizational decisions (eg, is consulted by senior leadership to make key decisions). * Tasks do… more
- Qualcomm (Santa Clara, CA)
- …transformation to help create a smarter, connected future for all. We are looking for ASIC Design Verification Engineers with strong CPU, ASIC design ... Engineering, or related field + Minimum 6+ years of design verification experience* Senior positions to be...Science, Engineering, or related field and 4+ years of ASIC design , verification, validation, integration, or related… more
- Amazon (Sunnyvale, CA)
- …Edge that is powering the latest generation of Echo devices is looking for a Senior SoC Design -STA Engineer to continue to innovate on behalf of our customers. ... STA, Crosstalk Delay and Crosstalk Noise analysis for digital ASIC /SoCs. * Full chip timing constraints development, full chip...& Route and other local/remote teams to address the design challenges in the context of timing sign-off. *… more
