- Qualcomm (San Diego, CA)
- …Inc. **Job Area:** Engineering Group, Engineering Group > ASICS Engineering **General Summary:** As a Timing Engineer , you will play a vital role in Timing ... and Tempus. + You will facilitate and drive STA methodology for Qualcomm using PT-SI, Tempus and best in...for STA timing sign off. + A timing Engineer should be able to understand… more
- Google (San Diego, CA)
- …technology process nodes. + Experience with ASIC design flows and methodology of static timing analysis. + Experience in extraction of design ... equivalent practical experience. + 5 years of technical experience in silicon timing closure and chip integration. + Experience with STA signoff constraint authoring… more
- Qualcomm (San Diego, CA)
- … ASIC /SoC design flows (micro-architecture, RTL design, verification, synthesis, timing /STA, UPF, CLP, LEC formal verification, DFT, physical design.) + Hands-on ... company in the world. Qualcomm is looking for bright ASIC engineers with excellent analytical and technical skills, and...performance, low power Memory Subsystem RTL Design, flows and methodology for high performance ASICs in sub-4nm process for… more
- Qualcomm (San Diego, CA)
- …Controller and Advanced Memory NoCs based Subsystem Design Team is looking for ASIC Design Engineers for the next generation high speed LPDDR/DDR memory subsystems.. ... such as CPU, GPU, DSP, Multimedia Processors and the engineer is expected to be responsible for enabling high...when integrated into the rest of the chip. Synthesis, Timing Closure, Physical Design Support, Gate Level Simulations, Power… more
- Qualcomm (San Diego, CA)
- …& large-scale software automation enablement. Excellent understanding of statistical Liberty timing , power model and Front-end Verilog views and tools. Silicon ... with industry standard chip design tools and design flows for Static Timing Analysis, Spice / Fast spice simulation, Synthesis, DFT, Power Analysis **Education… more
- Qualcomm (San Diego, CA)
- …drive development of advanced methodologies in die-level IR drop, STA, and power. The engineer should be proficient in static timing analysis using the Synopsys ... IR drop analysis and optimization is also helpful. The engineer is expected to propose, develop, and validate new...interaction of IR drop and STA ⦁ Develop physical-aware timing and IR drop ECO solutions ⦁ Collaborate closely… more
- Qualcomm (San Diego, CA)
- …controller and digital power meter. + Perform RTL design, simulation, synthesis, timing analysis, lint check, clock domain crossing check, conformal low power check, ... cycle from RTL to GDS. Analyze how a new methodology will affect different phases of the design/verification cycle...+ 3 years of experience doing low power digital ASIC design. + Familiar with ASIC front-end… more
- Qualcomm (San Diego, CA)
- …drive CPU timing closure for Oryon CPU Cores. As a CPU Physical Design Timing Engineer , you will work with microarchitecture and RTL design team to develop ... STA native tools and also useful in enabling CPU timing infrastructure and methodology impacting multiple CPU...Layout Parasitic Extraction, feed through handling, + Knowledge of ASIC back-end design flows and methods and tools (ICC2,… more
- Qualcomm (San Diego, CA)
- …as the PC and the Data Center markets. Qualcomm is looking for bright ASIC engineers with excellent analytical and technical skills. Besides solid ASIC and/or ... fast-paced SoC team responsible for RTL Design, flows and methodology for high performance ASICs in the latest process...new projects are coming up, it is a wonderful timing to join our team and take part in… more
- Qualcomm (San Diego, CA)
- …independently with little supervision. **Preferred Qualifications:** + Strong familiarity with Static Timing Analysis and Physical Design tools & methodology . + ... ASICS Engineering **General Summary:** As a SoC Power/Performance Post-Si Validation & Emulation Engineer , you will be a vital member of our Global SoC System… more
- Qualcomm (San Diego, CA)
- …flows + Familiarity with Verilog and RTL design + Good understanding of static timing analysis and timing methodology + Proficient in scripting, preferably ... Engineering **General Summary:** Qualcomm's is seeking a digital design engineer for the Design Technology team. The candidate should...with STA tools such as PTSI and with the ASIC design flow from synthesis through P&R. This candidate… more
- Qualcomm (San Diego, CA)
- …connected future for all. QCT Memory Controller Design Team is looking for ASIC Design Engineers for the next generation high speed DDR Controllers. The front ... system such as CPU, DSP, Multimedia Processors and the engineer is expected to be responsible for enabling high...when integrated into the rest of the chip. Synthesis, Timing Closure, Physical Design Support, Gate Level Simulations, Power… more