- Qualcomm (San Diego, CA)
- …Inc. **Job Area:** Engineering Group, Engineering Group > ASICS Engineering **General Summary:** As a Timing Engineer , you will play a vital role in Timing ... and Tempus. + You will facilitate and drive STA methodology for Qualcomm using PT-SI, Tempus and best in...for STA timing sign off. + A timing Engineer should be able to understand… more
- Google (San Diego, CA)
- …technology process nodes. + Experience with ASIC design flows and methodology of static timing analysis. + Effective skills with scripting languages ... equivalent practical experience. + 5 years of technical experience in silicon timing closure and chip integration. + Experience with STA signoff constraint authoring… more
- Qualcomm (San Diego, CA)
- … ASIC /SoC design flows (micro-architecture, RTL design, verification, synthesis, timing /STA, UPF, CLP, LEC formal verification, DFT, physical design.) + Hands-on ... company in the world. Qualcomm is looking for bright ASIC engineers with excellent analytical and technical skills, and...performance, low power Memory Subsystem RTL Design, flows and methodology for high performance ASICs in sub-4nm process for… more
- Qualcomm (San Diego, CA)
- …Controller and Advanced Memory NoCs based Subsystem Design Team is looking for ASIC Design Engineers for the next generation high speed LPDDR/DDR memory subsystems.. ... such as CPU, GPU, DSP, Multimedia Processors and the engineer is expected to be responsible for enabling high...when integrated into the rest of the chip. Synthesis, Timing Closure, Physical Design Support, Gate Level Simulations, Power… more
- Amazon (San Diego, CA)
- …both logic and physical synthesis flow for various technology nodes. * Work with the ASIC design and DFT teams to understand the design and create timing ... the best PPA for all blocks. * Lead the timing sign-off for the post P&R database. * Ensure...or equivalent experience. * 7+ years of experience in ASIC implementation, ie, synthesis, STA and working with P&R… more
- Qualcomm (San Diego, CA)
- …drive development of advanced methodologies in die-level IR drop, STA, and power. The engineer should be proficient in static timing analysis using the Synopsys ... IR drop analysis and optimization is also helpful. The engineer is expected to propose, develop, and validate new...interaction of IR drop and STA ⦁ Develop physical-aware timing and IR drop ECO solutions ⦁ Collaborate closely… more
- Qualcomm (San Diego, CA)
- …as the PC and the Data Center markets. Qualcomm is looking for bright ASIC engineers with excellent analytical and technical skills. Besides solid ASIC and/or ... fast-paced SoC team responsible for RTL Design, flows and methodology for high performance ASICs in the latest process...new projects are coming up, it is a wonderful timing to join our team and take part in… more
- Qualcomm (San Diego, CA)
- …at connectivity module level, and chip level modes. You will assist with the timing closure of your designs. You will make regular contributions to the overall ... improvement in design methodology to drive productivity and initiatives All Qualcomm employees...Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.… more
- Qualcomm (San Diego, CA)
- …connected future for all. QCT Memory Controller Design Team is looking for ASIC Design Engineers for the next generation high speed DDR Controllers. The front ... system such as CPU, DSP, Multimedia Processors and the engineer is expected to be responsible for enabling high...when integrated into the rest of the chip. Synthesis, Timing Closure, Physical Design Support, Gate Level Simulations, Power… more