- Meta (Sunnyvale, CA)
- …on Chip (SoC) and IP for data center applications. **Required Skills:** ASIC Implementation Engineer - Static Verification Responsibilities: 1. Perform Flat ... **Summary:** Meta is hiring ASIC Implementation Engineers within our Infrastructure organization. We...with the Designers to create waivers. 4. Perform RTL DFT Analysis and improve the DFT coverage… more
- Palo Alto Networks (Santa Clara, CA)
- …networking IP and backend + Technical expertise on the entire ASIC design flow-architecture, logic design, RTL coding, verification , FPGA validation, ... BSEE/MSEE required, 10+ year industrial experience + Minimum of 10 years ASIC design/ verification and 5 years of ASIC management experience required,… more
- Cisco (San Jose, CA)
- …service provider networks. Cisco's silicon team provides a unique experience for ASIC engineers by combining the resources offered by a large multi-geography silicon ... breadth of growth opportunities that working in a smaller ASIC team can provide. You will work with exceptional...fullchip SDCs and work with the Physical Design and DFT teams to close fullchip timing in multiple timing… more
- Cisco (San Jose, CA)
- …service provider networks. Cisco's silicon team provides a unique experience for ASIC engineers by combining the resources offered by a large multi-geography silicon ... breadth of growth opportunities that working in a smaller ASIC team can provide. You will work with exceptional...oversees fullchip SDCs and works with physical design and DFT teams to close fullchip timing in multiple timing… more
- Cisco (San Jose, CA)
- …* Help define, evolve, and support our design methodology. * Collaborate with the verification , PD, DFT , Package and SW teams to develop next generation ASICs. ... will engage in dynamic collaboration with Senior micro-architects, designers, verification engineers and interact with cross-functional software and product teams,… more
- Amazon (Cupertino, CA)
- …Our custom chips, accelerators, and software stacks enable us to take on technical challenges that have never been seen before, and deliver results that help ... scale and rapid integration of emergent technologies. We're looking for an ASIC Design Eengineer to help us trail-blaze new technologies and architectures, while… more
- Amazon (Cupertino, CA)
- …distribution, timing optimization, place and route, power integrity analysis, and physical verification * Write Tcl or PERL scripts to improve physical design flows ... and methods * Collaborate with RTL, DFT designers to ensure high quality design implementation Basic Qualifications - Enrolled in a Bachelors' degree program or… more
- Broadcom (San Jose, CA)
- …with GLS with & without parasitic annotated simulations + Prior experience in verification of the DFT design, architecture, and microarchitecture + Experience in ... this highly visible role you will be working on ASIC for data center connectivity applications.Qualifications include: + BSc...developing verification environments for various DFT patterns like,… more
- Meta (Sunnyvale, CA)
- …AXI, APB, I3C, SPI, UART, etc 16. Experience using C for system verification 17. Experience in DFT /Testability requirement definition and understanding of test ... research silicon to demonstrate and integrate advanced IP and AI accelerators into SOC/ ASIC solutions to enable in-system testing and prototyping. The goal is to… more
- Cisco (San Jose, CA)
- …partner organizations such as the Corporate Hardware Group to bring complex Cisco ASIC & Switch products to market. You will also engage closely with engineering ... bring-up and diagnostics teams, test & verification teams, and Product Quality teams to identify and...the NPI or Production processes. Your Impact As a Technical Leader in Silicon Reliability, you will play a… more
- Google (Sunnyvale, CA)
- …degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field, or equivalent practical experience. + 7 years of experience ... static timing (ie, full chip timing signoff ownership, constraint authoring and verification , full chip static timing analysis and timing ECO creation, timing… more
- Amazon (Cupertino, CA)
- …Design from RTL-to-GDSII - Understanding of other sign-off activities (ir/em, physical verification , timing closure, DFT ) - 3+ years of scripting experience ... Amazon's leadership principles requirements for this role - Meets/exceeds Amazon's functional/ technical depth and complexity for this role Amazon is an equal… more