- SLAC National Accelerator Laboratory (Menlo Park, CA)
- …(LCLS) Engineering Division at the SLAC National Accelerator Laboratory seeks a mechanical engineer to lead the Lasers and Timing Systems Engineering Department. ... Lasers and Timing Systems Engineering Department Head Job ID 6025...perspective, the department supplies engineering support to design and test proof of principal capabilities and works closely with… more
- Silicon Valley Power (Santa Clara, CA)
- …not meet the Education minimum qualifications for this position. 02 Please indicate which Senior Engineer (Civil) position you are interested in applying for. + ... ** Senior Civil Engineer ** Print (https://www.governmentjobs.com/careers/cityofsantaclaraca/jobs/newprint/4420027) ...traffic control devices. + Develop and review traffic signal timing parameters and coordination timing plans; +… more
- BAE Systems (San Jose, CA)
- …Other incentives may be available based on position level and/or job specifics. ** Senior Principal Front End ASIC Design Engineer (Hybrid)** **105684BR** EEO ... of a large company. We are looking for a senior level chip designer who has strong proficiency in...both + ASIC design- performing architecture design, RTL coding/simulation, timing closure at layout phase + Verification- executing testbench… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior ASIC Design Engineer for Memory Controllers. As a Senior Designer at NVIDIA, you'll join a group of hardworking engineers to ... micro-architecture and design including RTL design, synthesis, functional verification and timing analysis using groundbreaking CAD tools and using the latest… more
- TrustPoint (Mountain View, CA)
- …anti-jam capabilities. The improvements will support US Government position and timing service resiliency as well as enable next-generation commercial applications ... with our microsatellite based commercial infrastructure and innovative positioning and timing services. The Position With locations outside Washington DC and in… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a motivated Senior Circuit Design Engineer to join our dynamic and growing team. If you are looking for a challenging and exciting role in ... improving the netlist and timing quality of our designs and if you are...automated tools. + Create prototypes of patentable ideas on test chips and drive them to be deployed across… more
- NVIDIA (Santa Clara, CA)
- We are now hiring for a Senior Logic and Digital Circuit Design Engineer ! NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in ... algorithms. You'll then implement the RTL in SystemVerilog, define test cases that will deeply verify the design and...define and build constraints for synthesis and drive for timing closure. In addition to RTL design, you'll need… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a motivated Senior Circuit Design Engineer to join our dynamic and growing team. If you are looking for a challenging and exciting role in ... improving the netlist and timing quality of our designs and if you are...the designs. + Create prototypes of patentable ideas on test chips and drive them to be deployed across… more
- Vector Atomic (Pleasanton, CA)
- …company, Vector Atomic is the place for you! Position Summary We are seeking a Senior FPGA Engineer to join our team and contribute to the development of ... issues to ensure robust board layouts + Create RTL, test benches, and EDA support files to meet performance...and/or Altera FPGA/SoCs + Proficiency in writing physical and timing constraints (SDC) for high clock rate FPGAs +… more
- NVIDIA (Santa Clara, CA)
- We are looking for a Senior Mixed-Signal/Analog/IO Circuit Design Engineer - someone who is excited to join a rapidly growing team of creative circuit design ... and Latch-Up requirements + Possess an understanding of system-level timing budgets, specs, and analysis + Working Knowledge of...plus + Hands-on experience of silicon debug with Lab test and measurement equipment is a plus + A… more
- NVIDIA (Santa Clara, CA)
- … Test Equipment (ATE) + Lead multi-functional efforts with DFx, Design, Timing , Test , Foundry to root-cause complicated technical problems + Find creative ... latest architecture designs to market! + Identify and implement test processes to improve manufacturing efficiency for our latest...to influence future ASIC designs to improve product quality, test coverage to drive yields up and reduce waste… more
- NVIDIA (Santa Clara, CA)
- …required. + Experience in Spice simulation and analysis. + Understanding of timing closure, interconnect design, and custom circuits are required. + Understanding of ... power circuits, eg power gating, decaps, multi-vt is required. + Understanding of Design-for- test (DFT) and logic design is a plus. + Proficiency in scripting… more
- NVIDIA (Santa Clara, CA)
- …solutions and detailed transistor-level analysis. + Create prototypes of patentable ideas on test chips and drive them to be deployed across the entire line of ... + Hands on experience running Spice simulations, EM/IR analysis, and static timing analysis/closure is required. + Basic understanding and experience working with… more
- Vector Atomic (Pleasanton, CA)
- …is building quantum devices for applications including GPS-free navigation and timing , geophysical exploration, and telecommunications. We are focused on delivering ... improve signal integrity. + Assist with board "bring-up" and debugging. Develop test scripts and documentation to assist with validation. + Collaborate with software… more
- SpaceX (Sunnyvale, CA)
- …to support critical milestones COMPENSATION & BENEFITS: Pay range: ASIC/FPGA Design Engineer / Senior : $170,000.00 - $230,000.00/per year Your actual level and ... Sr. DDR IP Design Engineer (Silicon Engineering) at SpaceX Sunnyvale, CA SpaceX...internet to millions of users worldwide. We design, build, test , and operate all parts of the system -… more
- SpaceX (Sunnyvale, CA)
- …hours and weekends as needed COMPENSATION AND BENEFITS: Pay range: Physical Design Engineer / Senior : $170,000.00 - $230,000.00/per year Your actual level and base ... Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering) at SpaceX Sunnyvale, CA SpaceX...internet to millions of users worldwide. We design, build, test , and operate all parts of the system -… more
- NVIDIA (Santa Clara, CA)
- We are now looking for a Senior Physical Design Engineer in our Circuits Solutions Group! NVIDIA has been redefining computer graphics, PC gaming, and ... automation, floorplan, power/clock distribution, IP and toplevel P&R, and timing closure. + Drive the physical implementation of custom...design flows. + Create prototypes of patentable ideas on test chips and drive them to be deployed across… more
- Amazon (Sunnyvale, CA)
- …unserved and underserved communities around the world. Come work at Amazon! The Role: As Senior Silicon ATE Test Engineer , you will engage with an ... an open collaborative peer environment. You'll be responsible for high-volume production test methodology for custom SoCs for Project Kuiper. You'll be part of… more
- Amazon (Cupertino, CA)
- …area requirements. - Develop micro-architecture, implement SystemVerilog RTL, and deliver synthesis/ timing clean design with constraints. - Perform lint and clock ... designers, verification teams, pre- and post-silicon validation teams, synthesis, timing and back-end teams to accomplish your tasks. You...assertions - Have good debug skills to analyze RTL test failures - Have a "Learn and Be Curious"… more