• Sr . Principal STA Solutions…

    Cadence Design Systems, Inc. (San Jose, CA)
    …bug fixes. Work on various aspects of physical design including timing analysis, place and route , extraction, spice etc. Job Responsibilities: . Perform Static ... Work on In-design timing ECO optimizations solutions with basic knowledge of Place and Route , Clock Tree, RC Extraction, power and UPF/CPF concepts. . Execute… more
    Cadence Design Systems, Inc. (03/01/24)
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  • Senior RTL to GDS Principal

    Cadence Design Systems, Inc. (San Jose, CA)
    …customers in the areas of Backend Digital Design Implementation and Signoff including Place and Route , Design Closure, and timing/power signoffGuide customers on ... with IC digital implementation flows and backend EDA tools including Place and Route , IR Drop, backend design timing and power closureExperience with advanced… more
    Cadence Design Systems, Inc. (04/27/24)
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  • Senior Physical Design Applications…

    Cadence Design Systems, Inc. (San Jose, CA)
    …+ Working with customers in one or more of the following areas: Synthesis, Place and Route , timing and power signoff. + Understanding and proliferating Cadence ... who want to make an impact on the world of technology. Principal Application Engineer responsible for providing pre-sales and post-sales technical support for… more
    Cadence Design Systems, Inc. (04/13/24)
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  • Mobile Chipset Engineer

    Qualcomm (Santa Clara, CA)
    …* 2+ years of work experience in a role requiring interaction with senior leadership (eg, Director level and above). ** Principal Duties and Responsibilities:** ... highly complex process flow from high-level design to synthesis, place and route , timing and power use,...influence over key organizational decisions (eg, is consulted by senior leadership to make key decisions). * Tasks do… more
    Qualcomm (05/11/24)
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  • Digital Design Engineer (Staff)

    Qualcomm (Santa Clara, CA)
    …* 1+ year of work experience in a role requiring interaction with senior leadership (eg, Director level and above). ** Principal Duties & Responsibilities:** ... of complex process flow from high-level design to synthesis, place and route , timing and power use,...influence over key organizational decisions (eg, is consulted by senior leadership to make key decisions). * Tasks do… more
    Qualcomm (04/20/24)
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  • Staff SOC Physical Design Engineer

    Qualcomm (Santa Clara, CA)
    …* 1+ year of work experience in a role requiring interaction with senior leadership (eg, Director level and above). ** Principal Duties & Responsibilities:** ... clock tree synthesis, placement, routing and timing ECOs. * Place and Route : Executing placement and routing...influence over key organizational decisions (eg, is consulted by senior leadership to make key decisions). * Tasks do… more
    Qualcomm (04/12/24)
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  • CPU Micro-architect/RTL Designer

    Qualcomm (Santa Clara, CA)
    …VHDL, etc.). * 10+ years of work experience with industry standard tools for synthesis place and/or route and design verification. * 10+ years of work experience ... * 1+ year of work experience in a role requiring interaction with senior leadership (eg, Director level and above). ** Principal Duties and Responsibilities:**… more
    Qualcomm (04/10/24)
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