- Meta (Sunnyvale, CA)
- **Summary:** Meta is hiring ASIC Formal Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in ... Post-Silicon teams towards creating a first-pass silicon success. **Required Skills:** ASIC Engineer , Formal Verification Responsibilities: 1. Provide… more
- Meta (Sunnyvale, CA)
- **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in ... teams towards creating a first-pass silicon success. **Required Skills:** ASIC Engineer , Network Design Verification ...or more of the following areas along with functional verification -SV Assertions, Formal , Emulation 12. Experience in… more
- Meta (Sunnyvale, CA)
- **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in ... teams towards creating a first-pass silicon success. **Required Skills:** ASIC Engineer , Design Verification Responsibilities:...or more of the following areas along with functional verification - SV Assertions, Formal , Emulation 14.… more
- Meta (Sunnyvale, CA)
- **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in ... and Post-Silicon teams towards creating a first-pass silicon success. **Required Skills:** ASIC Engineer , Design Verification Responsibilities: 1. Define and… more
- Meta (Sunnyvale, CA)
- **Summary:** Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in ... and Post-Silicon teams towards creating a first-pass silicon success. **Required Skills:** ASIC Engineer , Design Verification Responsibilities: 1. Define and… more
- Google (Mountain View, CA)
- Staff ASIC Design Verification Engineer , Platforms and Devices _corporate_fare_ Google _place_ Mountain View, CA, USA **Advanced** Experience owning outcomes ... emphasis on computer architecture. + 12 years of experience with building verification methodologies that span simulation, formal , emulation and FPGA… more
- Amazon (Sunnyvale, CA)
- …in the validation of ASIC implementations in Verilog/SystemVerilog . Run formal verification of complex blocks to ensure functional correctness . Work ... Matlab model : development or DV integration experience - Familiarity with formal verification techniques - Strong written and verbal skills Amazon is an equal… more
- SpaceX (Sunnyvale, CA)
- …of design blocks using Verilog/SystemVerilog + Familiar with UPF (unified power format), formal verification , and DRC rule checking experience + Ability to work ... ASIC /SOC DFT Engineer (Silicon Engineering) Sunnyvale,...weekends as needed COMPENSATION AND BENEFITS: Pay range: Design Verification Engineer /Level I: $130,000.00 - $155,000.00/per year… more
- Meta (Sunnyvale, CA)
- …complex SoC and IP for data center applications. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Architecture exploration 2. Micro-architecture ... **Summary:** Meta is hiring ASIC Design Engineers within our Infrastructure organization to...Peripheral Subsystems 13. Experience with Synthesis, Timing Closure and Formal Verification Methodology 14. Master's or PhD… more
- Meta (Sunnyvale, CA)
- …as machine learning, video transcoding and network acceleration. **Required Skills:** ASIC Engineer , Design Responsibilities: 1. Architecture exploration 2. ... **Summary:** Meta is hiring ASIC Design Engineers within our Infrastructure organization to...Peripheral Subsystems 9. Experience with Synthesis, Timing Closure and Formal Verification Methodology 10. Master's or PhD… more
- Amazon (Sunnyvale, CA)
- …Familiarity with UVM and Matlab. . Ability to write assertions and exposure to Formal verification Amazon is an equal opportunity employer and does not ... work at Amazon! We're hiring a Sr. Modem Design Engineer within a high performance ASIC design...solutions, and meeting the power objectives . Create standalone verification test bench to verify the correctness of your… more
- Meta (Sunnyvale, CA)
- …click "Apply to Job" online on this web page. **Required Skills:** ASIC Engineer , Implementation Responsibilities: 1. Run logic/physical synthesis using advanced ... at RTL & gate level and identify power reduction opportunities. 4. Run formal verification checks between RTL & gate level netlist and debug aborts, inconclusive… more
- Cisco (San Jose, CA)
- …Cadence) + Experience with Spyglass CDC and glitch analysis + Experience using Formal Verification : Synopsys Formality and Cadence LEC. + Experience with ... ASIC Design Technical Leader - Design & Timing...customer shipments **Your Impact** You are a diligent Design/SDC Engineer with strong analytical skills and a deep understanding… more
- Amazon (Sunnyvale, CA)
- …methodology - Develop, regress and deploy digital implementation flows including Synthesis and Formal Verification - Enable digital design teams to meet PPA ... Come work at Amazon! The Role: As Senior CAD Engineer you will be responsible for installing and maintaining...and debugging techniques - Familiar with basic Synthesis and Formal Verification methodology and flow development experience… more
- Arrow Electronics (Mountain View, CA)
- **Position:** Design Verification Engineer **Job Description:** Principal Accountabilities * Responsible for architecting Verification Environment for ... ASIC SoC and providing verification support from defining verification plan to...technical specification documents * Implement and maintain integrated end-to-end formal verification flow for the formal… more
- ManpowerGroup (Mountain View, CA)
- …Mountain View, CA **What's the Job?** + Focus on verifying the design of the ASIC /SoC using simulation, formal verification , and emulation. + Utilize tools ... a leader in technology innovation, is seeking a Silicon Verification Engineer to join their team. As...digital design principles and computer architecture. + Experience with formal verification tools and methodologies. **What's in… more
- Amazon (Cupertino, CA)
- …tools (examples: Cadence, Mentor Graphics, Synopsys, or Others) develop flows for synthesis, formal verification , floor planning, bus / pin planning, place and ... massive scale and rapid integration of emergent technologies. We're looking for an ASIC Physical Design Engineer to help us trail-blaze new technologies and… more
- Amazon (Cupertino, CA)
- …massive scale and rapid integration of emergent technologies. We're looking for an ASIC Physical Design Methodology Engineer to help us trail-blaze new ... physical design, and methodologies including synthesis, place and route, STA, IR, formal and physical verification . - Demonstrated level of expertise in PD… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …flow, preferably on Genus and Innovus + Experience in Logic Design and Synthesis, Formal Verification , Low Power design, Physical Design and Timing Closure for ... You will be a highly motivated, optimistic, and energetic engineer with a good appreciation of ASIC design methodologies from RTL to GDSII with a strong… more
- Amazon (Cupertino, CA)
- …physical design flows, and methodologies including synthesis, place and route, STA, formal verification . - Proven track record of delivering metric driven ... AI services for our customers' businesses. We are seeking experienced Physical Design Engineer to build the next generation of our cloud server platforms. Our… more