- Broadcom (San Jose, CA)
- …Sign-In before you apply.** **Job Description:** **Broadcom is looking for a senior level RTL synthesis engineer . In this highly visible role, you will ... years of experience in Physical design.** + **Expert in Logic/Physical Synthesis using advanced optimization techniques and generating optimized Gate Level Netlist… more
- Amazon (Sunnyvale, CA)
- …Fire TV and Amazon Echo. What will you help us create? The Role: As a Senior RTL Design Engineer , you will be part of an advanced architecture team that is ... - Develop detailed design specifications and documentation - Perform RTL coding and synthesis - Work with Partners/Supplier to optimize and customize their… more
- Amazon (Sunnyvale, CA)
- …tablets, Fire TV and Amazon Echo. What will you help us create? The Role: As an RTL Design Engineer , you will be part of an advanced architecture team that is ... - Develop detailed design specifications and documentation - Perform RTL coding and synthesis - Work with Partners/Supplier to optimize and customize their… more
- Broadcom (San Jose, CA)
- …apply.** **Job Description:** **Broadcom is looking for a high-speed DSP SerDes RTL designer. Qualifications include:** + **MS or PhD in Electrical Engineering or ... years of experience in high speed ADC based SerDes RTL design.** + **Proficient with Verilog-HDL/System Verilog coding for...and cost over the project lifetime.** + **Experience in synthesis , CDC, static timing analysis.** + **Exposure to SDF… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …but is not limited to: + Digital microarchitecture definition and documentation + RTL logic design, debug and functional verification + Strong background in DSP and ... of Lint checks and proper resolution of errors + Understanding synthesis timing constraints, static timing analysis and constraint development + Understanding… more
- Microsoft Corporation (Mountain View, CA)
- …augmented reality. We are looking for a ** ** **Principal** **Design** **Technical Engineer ** to work in the dynamic Microsoft Artificial Intelligence System on Chip ... You will be responsible for developing and maintaining the RTL design flows and methodologies for our cutting edge...tools, flows and methodologies such as Lint, CDC, RDC, Synthesis + 8+ years of experience in architecting and… more
- Meta (Sunnyvale, CA)
- …"Apply to Job" online on this web page. **Required Skills:** ASIC Engineer , Implementation Responsibilities: 1. Run logic/physical synthesis using advanced ... and corresponding reset sequence for RDC. 10. Develop timing constraints for RTL - synthesis and PrimeTime-STA for blocks and top-level including SOC. 11. Analyze… more
- Google (Mountain View, CA)
- …IP design. + Experience with methodologies for low power estimation, timing closure, synthesis . + Experience with methodologies for RTL quality checks (eg, Lint, ... ASIC Engineer , IP Design, Silicon _corporate_fare_ Google _place_ Mountain...RTL development (SystemVerilog), debug functional/performance simulations. + Perform RTL quality checks including Lint, CDC, Synthesis ,… more
- Amazon (Cupertino, CA)
- …power, performance or area requirements. - Develop micro-architecture, implement SystemVerilog RTL , and deliver synthesis /timing clean design with constraints. - ... you will implement and deliver high performance, area and power efficient RTL to achieve design targets and specifications. - Analyze design, microarchitecture or… more
- ManpowerGroup (Mountain View, CA)
- Our client, a leader in the technology sector, is seeking a Hardware Design Engineer 5 to join their team. As a Hardware Design Engineer 5, you will be part of ... align successfully in the organization. **Job Title:** Hardware Design Engineer 5 **Location:** Austin, TX and Mountain View, CA...**Pay Range:** **What's the Job?** + Design and implement RTL for image and video processing IP blocks. +… more
- Amazon (Sunnyvale, CA)
- …high-speed broadband connectivity. Come work at Amazon! The Role: As Senior CAD Engineer you will be responsible for installing and maintaining EDA tools and flows ... processes - Develop, regress, and deploy digital front end flows including RTL static checks and design verification methodology - Develop, regress and deploy… more
- Amazon (Cupertino, CA)
- …integration of emergent technologies. We're looking for an ASIC Physical Design Engineer to help us trail-blaze new technologies and architectures, while ensuring ... the right trade-offs. Key job responsibilities - Work with RTL /logic designers to drive architectural feasibility studies, explore power-performance-area tradeoffs… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …R&D teams to win opportunities* Run Verilog simulations to enable IP benchmarking* Run RTL synthesis for area and timing analysis* Present IP demos to customers* ... an impact on the world of technology. Senior Applications Engineer - DDR Design IPJob Location: San Jose, CAJob...presales of DDR IP by generating collateral through simulations, synthesis and publications. As you grow into more senior… more
- Cadence Design Systems, Inc. (San Jose, CA)
- …on the world of technology. This opportunity is for an engagement focused Product Engineer (PE) in the Digital and Signoff Group (DSG) at Cadence. The Cadence DSG ... You will be a highly motivated, optimistic, and energetic engineer with a good appreciation of ASIC design methodologies...with a good appreciation of ASIC design methodologies from RTL to GDSII with a strong history of self-improvement… more
- Amazon (Cupertino, CA)
- …of emergent technologies. We're looking for an ASIC Physical Design Methodology Engineer to help us trail-blaze new technologies and architectures, while ensuring ... compute and storage utilization for physical design work. Interface directly with RTL , Physical Design, Package Design, DFT teams to improve methodologies and… more
- Google (Mountain View, CA)
- …design concepts, and languages such as Verilog or SystemVerilog. + Experience with logic synthesis techniques to optimize RTL code, performance and power as well ... TPU Design Engineer , Silicon _corporate_fare_ Google _place_ Mountain View, CA,...ensure functionality of the design. + Provide input on synthesis , timing closure, and Physical Design of digital blocks.… more
- Microsoft Corporation (Mountain View, CA)
- …working on Intellectual Property (IP) microarchitecture specification, Register Transfer Level ( RTL ) design, synthesis /Lint/CDC/FEV and System on Chip (SOC) ... to help achieve that mission. We are looking for a **Senior** **Design Engineer ** to work in the dynamic Microsoft Artificial Intelligence System on Chip (AISoC)… more
- Amazon (Cupertino, CA)
- …features, power consumption, performance, and area requirements * Implement SystemVerilog RTL , and deliver synthesis and timing-clean designs with appropriate ... and making the right trade-offs. Key job responsibilities As an ASIC Design Engineer , you will: * Develop and implement high-performance, area and power-efficient … more
- Meta (Sunnyvale, CA)
- …9. Experience with top level integration using automation tools. 10. Experience in RTL coding, synthesis and/or SoC Integration. 11. Experience in digital design ... **Summary:** As a Digital Design Engineer at Meta Reality Labs, you will work...plan development and verification. 3. Define timing constraints, run synthesis and static timing analysis. 4. Support the test… more
- Amazon (Cupertino, CA)
- …AI services for our customers' businesses. We are seeking experienced Physical Design Engineer to build the next generation of our cloud server platforms. Our ... reports for project tracking and visualizing QoR/stats - Interface directly with RTL , Physical Design, Package Design, DFT and other teams to improve methodologies… more